A 900 Mb/s bidirectional signaling scheme. - Randy Mooney; Charles Dike; Shekhar Borkar (IEEE J. Solid State Circuits, 1995)

An 8-Gb/s simultaneous bidirectional link with on-die waveform capture. - Bryan Casper; Aaron Martin; James E. Jaussi; Joe Kennedy 001; Randy Mooney (IEEE J. Solid State Circuits, 2003)

Analysis of PLL clock jitter in high-speed serial links. - Pavan Kumar Hanumolu; Bryan Casper; Randy Mooney; Gu-Yeon Wei; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Jitter in high-speed serial and parallel links. - Pavan Kumar Hanumolu; Bryan Casper; Randy Mooney; Gu-Yeon Wei; Un-Ku Moon (ISCAS (4), 2004)

8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew. - James E. Jaussi; Ganesh Balamurugan; David R. Johnson; Bryan Casper; Aaron Martin; Joseph T. Kennedy; Naresh R. Shanbhag; Randy Mooney (IEEE J. Solid State Circuits, 2005)

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. - Joseph T. Kennedy; Randy Mooney; Robert Ellis; James E. Jaussi; Shekhar Borkar; Jung-Hwan Choi; Jae-Kwan Kim 003; Chan-Kyong Kim; Woo-Seop Kim; Chang-Hyun Kim; Soo-In Cho; Steffen Loeffler; et al. (IEEE J. Solid State Circuits, 2005)

A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B. - Bryan Casper; James E. Jaussi; Frank O'Mahony; Mozhgan Mansuri; K. Canagasaby; Joseph T. Kennedy; E. Yeung; Randy Mooney (ISSCC, 2006)

A 20Gb/s Embedded Clock Transceiver in 90nm CMOS. - Bryan Casper; James E. Jaussi; Frank O'Mahony; Mozhgan Mansuri; K. Canagasaby; Joe Kennedy 001; Randy Mooney (ISSCC, 2006)

Strong injection locking of low-Q LC oscillators. - Mozhgan Mansuri; Frank O'Mahony; Ganesh Balamurugan; James E. Jaussi; Joseph T. Kennedy; Sudip Shekhar; Randy Mooney; Bryan Casper (CICC, 2008)

Session 10 - Panel discussion Sure, Moore's Law can continue, but should it. - David A. Sunderland; Kazuyuki Kawauchi; John Kent; Randy Mooney; Chuck Moore; Clark T.-C. Nguyen (CICC, 2008)

A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS. - Frank O'Mahony; Sudip Shekhar; Mozhgan Mansuri; Ganesh Balamurugan; James E. Jaussi; Joseph T. Kennedy; Bryan Casper; David J. Allstot; Randy Mooney (ISSCC, 2008)

A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS. - Ganesh Balamurugan; Joseph T. Kennedy; Gaurab Banerjee; James E. Jaussi; Mozhgan Mansuri; Frank O'Mahony; Bryan Casper; Randy Mooney (IEEE J. Solid State Circuits, 2008)

Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver. - Sudip Shekhar; Ganesh Balamurugan; David J. Allstot; Mozhgan Mansuri; James E. Jaussi; Randy Mooney; Joseph T. Kennedy; Bryan Casper; Frank O'Mahony (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS. - Frank O'Mahony; Joseph T. Kennedy; James E. Jaussi; Ganesh Balamurugan; Mozhgan Mansuri; Clark Roberts; Sudip Shekhar; Randy Mooney; Bryan Casper (ISSCC, 2010)

A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS. - Frank O'Mahony; James E. Jaussi; Joseph T. Kennedy; Ganesh Balamurugan; Mozhgan Mansuri; Clark Roberts; Sudip Shekhar; Randy Mooney; Bryan Casper (IEEE J. Solid State Circuits, 2010)

A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS. - Mozhgan Mansuri; James E. Jaussi; Joseph T. Kennedy; Tzu-Chien Hsueh; Sudip Shekhar; Ganesh Balamurugan; Frank O'Mahony; Clark Roberts; Randy Mooney; Bryan Casper (ISSCC, 2013)

A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS. - Mozhgan Mansuri; James E. Jaussi; Joseph T. Kennedy; Tzu-Chien Hsueh; Sudip Shekhar; Ganesh Balamurugan; Frank O'Mahony; Clark Roberts; Randy Mooney; Bryan Casper (IEEE J. Solid State Circuits, 2013)

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS. - James E. Jaussi; Ganesh Balamurugan; Sami Hyvonen; Tzu-Chien Hsueh; Tawfiq Musah; Gökçe Keskin; Sudip Shekhar; Joseph T. Kennedy; Shreyas Sen; Rajesh Inti; Mozhgan Mansuri; Michael Leddige; et al. (ISSCC, 2014)

A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS. - Tawfiq Musah; James E. Jaussi; Ganesh Balamurugan; Sami Hyvonen; Tzu-Chien Hsueh; Gokce Keskin; Sudip Shekhar; Joseph T. Kennedy; Shreyas Sen; Rajesh Inti; Mozhgan Mansuri; Michael Leddige; et al. (IEEE J. Solid State Circuits, 2014)