Rationale for a 3D heterogeneous multi-core processor. - Eric Rotenberg; Brandon H. Dwiel; Elliott Forbes; Zhenqian Zhang; Randy Widialaksono; Rangeen Basu Roy Chowdhury; Nyunyi M. Tshibangu; Steve Lipa; W. Rhett Davis; Paul D. Franzon (ICCD, 2013)

Leveraging 3D-IC for on-chip timing uncertainty measurements. - Randy Widialaksono; Wenxu Zhao; W. Rhett Davis; Paul D. Franzon (3DIC, 2014)

Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor. - Elliott Forbes; Zhenqian Zhang; Randy Widialaksono; Brandon H. Dwiel; Rangeen Basu Roy Chowdhury; Vinesh Srinivasan; Steve Lipa; Eric Rotenberg; W. Rhett Davis; Paul D. Franzon (Hot Chips Symposium, 2015)

Reuse-Based Optimization for Prebond and Post-Bond Testing of 3-D-Stacked ICs. - Mukesh Agrawal 001; Krishnendu Chakrabarty; Randy Widialaksono (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Physical design of a 3D-stacked heterogeneous multi-core processor. - Randy Widialaksono; Rangeen Basu Roy Chowdhury; Zhenqian Zhang; Joshua Schabel; Steve Lipa; Eric Rotenberg; W. Rhett Davis; Paul D. Franzon (3DIC, 2016)

H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor. - Vinesh Srinivasan; Rangeen Basu Roy Chowdhury; Elliott Forbes; Randy Widialaksono; Zhenqian Zhang; Joshua Schabel; Sungkwan Ku; Steve Lipa; Eric Rotenberg; W. Rhett Davis; Paul D. Franzon (ICCD, 2017)