Continuing education in microprocessors: Use of software simulators. - Ranga Vemuri; J. V. Cornacchio (COMPSAC, 1978)

Data flow graph partitioning to reduce communication cost. - Cris Koutsougeras; Christos A. Papachristou; Ranga Vemuri (MICRO, 1986)

On the notion of the normal form register-level structures and its applications in design-space exploration. - Ranga Vemuri (EURO-DAC, 1990)

Temporal Precondition Verification of Design Transformations. - Ranga Vemuri; Anuradha Sridhar (CAV, 1991)

Genetic synthesis: performance-driven logic synthesis using genetic evolution. - Ram Vemuri; Ranga Vemuri (Great Lakes Symposium on VLSI, 1991)

Distributed Design-Space Exploration for High-Level Synthesis Systems. - Rajiv Dutta; Jayanta Roy; Ranga Vemuri (DAC, 1992)

Finite state machine verification on MIMD machines. - Nand Kumar; Ranga Vemuri (EURO-DAC, 1992)

DSS: A Distributed High-Level Synthesis System. - Jayanta Roy; Nand Kumar; Rajiv Dutta; Ranga Vemuri (IEEE Des. Test Comput., 1992)

Performance Specification and Measurement. - Ram Mandayam; Ranga Vemuri (CHDL, 1993)

Performance Specification Using Attributed Grammars. - Ram Mandayam; Ranga Vemuri (DAC, 1993)

Experiences in Functional Validation of a High Level Synthesis System. - Ranga Vemuri; Paddy Mamtora; Praveen Sinha; Nand Kumar; Jayanta Roy; Raghu Vutukuru (DAC, 1993)

An Integrated Multicomponent Synthesis for MCMs. - Ranga Vemuri; Nand Kumar; Raghu Vutukuru; Prasad Subba Rao; Praveen Sinha; Ning Ren; Paddy Mamtora; Ram Mandayam; Ram Vemuri; Jayanta Roy (Computer, 1993)

High level profiling based low power synthesis technique. - Srinivas Katkoori; Nand Kumar; Ranga Vemuri (ICCD, 1995)

Transformations for functional verification of synthesized designs. - William L. Bradley; Ranga Vemuri (VLSI Design, 1995)

Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems. - Nand Kumar; Srinivas Katkoori; Leo Rader; Ranga Vemuri (IEEE Des. Test Comput., 1995)

Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. - Ranga Vemuri; R. Kalyanaraman (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Rapid Prototyping of Reconfigurable Coprocessors. - Naren Narasimhan; Vinoo Srinivasan; Madhavi Vootukuru; Jeffrey Walrath; Sriram Govindarajan; Ranga Vemuri (ASAP, 1996)

Hierarchical behavioral partitioning for multicomponent synthesis. - Vinoo Srinivasan; Nand Kumar; Ranga Vemuri (EURO-DAC, 1996)

Specification of Control Flow Properties for Verification of Synthesized VHDL Designs. - Naren Narasimhan; Ranga Vemuri (FMCAD, 1996)

Simulation based architectural power estimation for PLA-based controllers. - Srinivas Katkoori; Ranga Vemuri (ISLPED, 1996)

A Hierarchical Register Optimization Algorithm for Behavioral Synthesis. - Srinivas Katkoori; Ranga Vemuri; Jay Roy (VLSI Design, 1996)

Synchronous Controller Models for Synthesis from Communicating VHDL Processes. - Naren Narasimhan; Ranga Vemuri; Jay Roy (VLSI Design, 1996)

Performance Modeling Using PDL. - Ranga Vemuri; Ram Manday; Vijay Meduri (Computer, 1996)

A constructive method for data path area estimation during high-level VLSI synthesis. - Natesan Venkateswaran; Anurag Gupta; Srinivas Katkoori; Dinesh Bhatia; Ranga Vemuri (ASP-DAC, 1997)

Symbolic Evaluation of Performance Models for Tradeoff Visualization. - Jeffrey Walrath; Ranga Vemuri (DAC, 1997)

Cone-based clustering heuristic for list-scheduling algorithms. - Sriram Govindarajan; Ranga Vemuri (ED&TC, 1997)

Performance verification using partial evaluation and interval analysis. - Jeffrey Walrath; Ranga Vemuri; W. Bradley (ED&TC, 1997)

Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms. - Sriram Govindarajan; Ranga Vemuri (ICCD, 1997)

Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs. - Madhavi Vootukuru; Ranga Vemuri; Nand Kumar (VLSI Design, 1997)

RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. - Karam S. Chatha; Ranga Vemuri (CODES, 1998)

Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures. - Meenakshi Kaul; Ranga Vemuri (DATE, 1998)

Hardware Software Partitioning with Integrated Hardware Design Space Exploration. - Vinoo Srinivasan; Shankar Radhakrishnan; Ranga Vemuri (DATE, 1998)

An Effective Design System for Dynamically Reconfigurable Architectures. - Sriram Govindarajan; Iyad Ouaiss; Meenakshi Kaul; Vinoo Srinivasan; Ranga Vemuri (FCCM, 1998)

A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. - Nazanin Mansouri; Ranga Vemuri (FMCAD, 1998)

Automatic data path abstraction for verification of large scale designs. - Viresh Paruthi; Nazanin Mansouri; Ranga Vemuri (ICCD, 1998)

An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. - Iyad Ouaiss; Sriram Govindarajan; Vinoo Srinivasan; Meenakshi Kaul; Ranga Vemuri (IPPS/SPDP Workshops, 1998)

A Performance Modeling and Analysis Environment for Reconfigurable Computers. - Jeffrey Walrath; Ranga Vemuri (IPPS/SPDP Workshops, 1998)

A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. - Karam S. Chatha; Ranga Vemuri (ISSS, 1998)

Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns. - Karam S. Chatha; Ranga Vemuri (International Workshop on Rapid System Prototyping, 1998)

On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis System. - Naren Narasimhan; Ranga Vemuri (TPHOLs, 1998)

Constraint Allocation in Analog System Synthesis. - Nagu R. Dhanwada; Ranga Vemuri (VLSI Design, 1998)

A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining. - Vinoo Srinivasan; Ranga Vemuri (VLSI Design, 1998)

Architectural Power Estimation Based on Behavior Level Profiling. - Srinivas Katkoori; Ranga Vemuri (VLSI Design, 1998)

Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. - Nagu R. Dhanwada; Adrián Núñez-Aldana; Ranga Vemuri (ASP-DAC, 1999)

Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. - Alex Doboli; Adrián Núñez-Aldana; Nagu R. Dhanwada; Sree Ganesan; Ranga Vemuri (DAC, 1999)

An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. - Meenakshi Kaul; Ranga Vemuri; Sriram Govindarajan; Iyad Ouaiss (DAC, 1999)

Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis. - Nagu R. Dhanwada; Adrián Núñez-Aldana; Ranga Vemuri (DATE, 1999)

A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems. - Alex Doboli; Ranga Vemuri (DATE, 1999)

Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. - Meenakshi Kaul; Ranga Vemuri (DATE, 1999)

Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. - Nazanin Mansouri; Ranga Vemuri (DATE, 1999)

An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis. - Adrián Núñez-Aldana; Ranga Vemuri (DATE, 1999)

Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures. - Vinoo Srinivasan; Ranga Vemuri (FCCM, 1999)

Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures. - Vinoo Srinivasan; Ranga Vemuri (FPGA, 1999)

Hardware-Software Codesign for Dynamically Reconfigurable Architectures. - Karam S. Chatha; Ranga Vemuri (FPL, 1999)

Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops. - Abhijit Ghosh; Sandeep K. Lodha; Ranga Vemuri (Great Lakes Symposium on VLSI, 1999)

Accurate Resource Estimation Algorithms for Behavioral Synthesis. - Srinivas Katkoori; Ranga Vemuri (Great Lakes Symposium on VLSI, 1999)

A Methodology for Rapid Prototyping of Analog Systems. - Sree Ganesan; Ranga Vemuri (ICCD, 1999)

Formal Verification of Synthesized Analog Designs. - Abhijit Ghosh; Ranga Vemuri (ICCD, 1999)

A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications. - Alex Doboli; Ranga Vemuri (VLSI, 1999)

A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements. - Adrián Núñez-Aldana; Ranga Vemuri (VLSI, 1999)

Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures. - Meenakshi Kaul; Ranga Vemuri (IPPS/SPDP Workshops, 1999)

Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures. - Vinoo Srinivasan; Shankar Radhakrishnan; Ranga Vemuri; Jeffrey Walrath (IPPS/SPDP Workshops, 1999)

A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis. - Nagu R. Dhanwada; Adrián Núñez-Aldana; Ranga Vemuri (ISCAS (6), 1999)

An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems. - Karam S. Chatha; Ranga Vemuri (IEEE International Workshop on Rapid System Prototyping, 1999)

Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis. - Nagu R. Dhanwada; Adrián Núñez-Aldana; Ranga Vemuri (VLSI Design, 1999)

FAAR: A Router for Field-Programmable Analog Arrays. - Sree Ganesan; Ranga Vemuri (VLSI Design, 1999)

Towards a Specification Notation for High-Level Synthesis of Mixed-Signal and Analog Systems. - Alex Doboli; Ranga Vemuri (BMAS, 2000)

Technology Mapping and Retargeting for Field-Programmable Analog Arrays. - Sree Ganesan; Ranga Vemuri (DATE, 2000)

An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement. - Satish Ganesan; Ranga Vemuri (DATE, 2000)

Improving the Schedule Quality of Static-List Time-Constrained Scheduling. - Sriram Govindarajan; Ranga Vemuri (DATE, 2000)

Efficient Resource Arbitration in Reconfigurable Computing Environments. - Iyad Ouaiss; Ranga Vemuri (DATE, 2000)

Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS. - Sriram Govindarajan; Ranga Vemuri (FPL, 2000)

An approach to high-level synthesis system validation using formally verified transformations. - Rajesh Radhakrishnan; Elena Teica; Ranga Vemuri (HLDVT, 2000)

Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints. - Preetham Lakshmikanthan; Sriram Govindarajan; Vinoo Srinivasan; Ranga Vemuri (IPDPS Workshops, 2000)

A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems. - Alex Doboli; Nagu R. Dhanwada; Ranga Vemuri (ISCAS, 2000)

Scheduling for low power under resource and latency constraints. - Srinivas Katkoori; Ranga Vemuri (ISCAS, 2000)

Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. - Abhijit Ghosh; Ranga Vemuri (VLSI Design, 2000)

A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. - Sriram Govindarajan; Vinoo Srinivasan; Preetham Lakshmikanthan; Ranga Vemuri (VLSI Design, 2000)

Configurable Computing: Technology and Applications - Guest Editors' Introduction. - Ranga Vemuri; Randolph E. Harr (Computer, 2000)

An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling. - Karam S. Chatha; Ranga Vemuri (Des. Autom. Embed. Syst., 2000)

Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs. - Nazanin Mansouri; Ranga Vemuri (Formal Methods Syst. Des., 2000)

Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems. - Meenakshi Kaul; Ranga Vemuri (J. VLSI Signal Process., 2000)

Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems. - Sree Ganesan; Ranga Vemuri (ARVLSI, 2001)

Verification of Basic Block Schedules Using RTL Transformations. - Rajesh Radhakrishnan; Elena Teica; Ranga Vemuri (CHARME, 2001)

MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. - Karam S. Chatha; Ranga Vemuri (CODES, 2001)

Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints. - Alex Doboli; Ranga Vemuri (DAC, 2001)

Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems. - Sree Ganesan; Ranga Vemuri (DAC, 2001)

A regularity-based hierarchical symbolic analysis method for large-scale analog networks. - Alex Doboli; Ranga Vemuri (DATE, 2001)

Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. - Iyad Ouaiss; Ranga Vemuri (DATE, 2001)

On the verification of synthesized designs using automatically generated transformational witnesses. - Elena Teica; Rajesh Radhakrishnan; Ranga Vemuri (DATE, 2001)

Memory Synthesis for FPGA-Based Reconfigurable Computers. - Amit Kasat; Iyad Ouaiss; Ranga Vemuri (FPL, 2001)

Global memory mapping for FPGA-based reconfigurable systems. - Iyad Ouaiss; Ranga Vemuri (IPDPS, 2001)

Continous Wavelet Transform on Reconfigurable Meshes. - Yi Pan 001; Jie Li 002; Ranga Vemuri (IPDPS, 2001)

Hierarchical performance optimization for synthesis of linear analog systems. - Alex Doboli; Ranga Vemuri (ISCAS (5), 2001)

Library Binding for High-Level Synthesis of Analog Systems. - Sree Ganesan; Ranga Vemuri (VLSI Design, 2001)

Application Specific Macro Based Synthesis. - Sujatha Sundararaman; Sriram Govindarajan; Ranga Vemuri (VLSI Design, 2001)

Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis. - Naren Narasimhan; Elena Teica; Rajesh Radhakrishnan; Sriram Govindarajan; Ranga Vemuri (Formal Methods Syst. Des., 2001)

Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures. - V. Srinivasan; Sriram Govindarajan; Ranga Vemuri (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Guest editorial reconfigurable and adaptive VLSI systems. - Ranga Vemuri; Rajesh K. Gupta 001 (IEEE Trans. Very Large Scale Integr. Syst., 2001)

A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems. - Alex Doboli; Ranga Vemuri (DATE, 2002)

iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications. - Jawad Khan; Manish Handa; Ranga Vemuri (FPL, 2002)

Framework for Synthesis of Virtual Pipelines. - Srinivasan Dasasathyan; Rajesh Radhakrishnan; Ranga Vemuri (ASP-DAC/VLSI Design, 2002)

An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. - Ranga Vemuri; Srinivas Katkoori; Meenakshi Kaul; Jay Roy (ACM Trans. Design Autom. Electr. Syst., 2002)

Hardware-software partitioning and pipelined scheduling of transformative applications. - Karam S. Chatha; Ranga Vemuri (IEEE Trans. Very Large Scale Integr. Syst., 2002)

A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. - Madhubanti Mukherjee; Ranga Vemuri (ICCD, 2003)

MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators. - Hemanth Sampath; Ranga Vemuri (VLSI-SOC, 2003)

Adaptive Sampling and Modeling of Analog Circuit Performance Parameters. - Glenn Wolfe; Mengmeng Ding; Ranga Vemuri (VLSI-SOC, 2003)

A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs. - Manish Handa; Rajesh Radhakrishnan; Madhubanti Mukherjee; Ranga Vemuri (VLSI Design, 2003)

Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. - Alex Doboli; Ranga Vemuri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies. - Alex Doboli; Ranga Vemuri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Extraction and use of neural network models in automated synthesis of operational amplifiers. - Glenn Wolfe; Ranga Vemuri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

A Design Methodology for Self-Timed Event Logic Pipelines. - Xin Jia; Ranga Vemuri (ESA/VLSI, 2004)

Fast and accurate parasitic capacitance models for layout-aware. - Anuradha Agarwal; Hemanth Sampath; Veena Yelamanchili; Ranga Vemuri (DAC, 2004)

An efficient algorithm for finding empty space for online FPGA placement. - Manish Handa; Ranga Vemuri (DAC, 2004)

Accurate Estimation of Parasitic Capacitances in Analog Circuits. - Anuradha Agarwal; Hemanth Sampath; Veena Yelamanchili; Ranga Vemuri (DATE, 2004)

A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement. - Manish Handa; Ranga Vemuri (DATE, 2004)

Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. - Mukesh Ranjan; Wim Verhaegen; Anuradha Agarwal; Hemanth Sampath; Ranga Vemuri; Georges G. E. Gielen (DATE, 2004)

Area Fragmentation in Reconfigurable Operating Systems. - Manish Handa; Ranga Vemuri (ERSA, 2004)

A Portable Face Recognition System Using Reconfigurable Hardware. - Jawad Khan; Jayanthi Rajagopalan; Renqiu Huang; Ranga Vemuri (ERSA, 2004)

A Power-Performance Trade-off Methodology for Portable Reconfigurable Platforms. - Jawad Khan; Balasubramanian Sethuraman; Ranga Vemuri (ERSA, 2004)

An Integrated Online Scheduling and Placement Methodology. - Manish Handa; Ranga Vemuri (FPL, 2004)

Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs. - Renqiu Huang; Manish Handa; Ranga Vemuri (FPL, 2004)

A Dynamically Reconfigurable Asynchronous FPGA Architecture. - Xin Jia; Jayanthi Rajagopalan; Ranga Vemuri (FPL, 2004)

An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms. - Jawad Khan; Ranga Vemuri (FPL, 2004)

A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. - Raoul F. Badaoui; Hemanth Sampath; Anuradha Agarwal; Ranga Vemuri (ACM Great Lakes Symposium on VLSI, 2004)

Analysis and evaluation of a hybrid interconnect structure for FPGAs. - Renqiu Huang; Ranga Vemuri (ICCAD, 2004)

Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. - Ranga Vemuri; Glenn Wolfe (ICCAD, 2004)

Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems. - Madhubanti Mukherjee; Ranga Vemuri (ICCD, 2004)

Hardware Assisted Two Dimensional Ultra Fast Placement. - Manish Handa; Ranga Vemuri (IPDPS, 2004)

Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs. - Renqiu Huang; Ranga Vemuri (IPDPS, 2004)

Battery-efficient task execution on portable reconfigurable computing. - Balasubramanian Sethuraman; Jawad Khan; Ranga Vemuri (SoCC, 2004)

A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. - Alex Doboli; Nagu R. Dhanwada; Adrián Núñez-Aldana; Ranga Vemuri (ACM Trans. Design Autom. Electr. Syst., 2004)

An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. - Mengmeng Ding; Glenn Wolfe; Ranga Vemuri (ASP-DAC, 2005)

Using GALS architecture to reduce the impact of long wire delay on FPGA performance. - Xin Jia; Ranga Vemuri (ASP-DAC, 2005)

Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. - Huiying Yang; Mukesh Ranjan; Wim Verhaegen; Mengmeng Ding; Ranga Vemuri; Georges G. E. Gielen (ASP-DAC, 2005)

A combined feasibility and performance macromodel for analog circuits. - Mengmeng Ding; Ranga Vemuri (DAC, 2005)

Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. - Raoul F. Badaoui; Ranga Vemuri (DATE, 2005)

Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric. - Amitava Bhaduri; Ranga Vemuri (DATE, 2005)

A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling. - Mengmeng Ding; Ranga Vemuri (DATE, 2005)

An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms. - Jawad Khan; Ranga Vemuri (DATE, 2005)

The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture. - Xin Jia; Ranga Vemuri (FCCM, 2005)

PAHLS: Towards Run-Time Synthesis for FPGAs. - Renqiu Huang; Ranga Vemuri (FPL, 2005)

A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation. - Xin Jia; Ranga Vemuri (FPL, 2005)

Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes. - Jawad Khan; Ranga Vemuri (FPL, 2005)

Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. - Anuradha Agarwal; Glenn Wolfe; Ranga Vemuri (ACM Great Lakes Symposium on VLSI, 2005)

Moment-driven coupling-aware routing methodology. - Amitava Bhaduri; Ranga Vemuri (ACM Great Lakes Symposium on VLSI, 2005)

LiPaR: A light-weight parallel router for FPGA-based networks-on-chip. - Balasubramanian Sethuraman; Prasun Bhattacharya; Jawad Khan; Ranga Vemuri (ACM Great Lakes Symposium on VLSI, 2005)

Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. - Anuradha Agarwal; Ranga Vemuri (ICCAD, 2005)

Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. - Anuradha Agarwal; Ranga Vemuri (ICCD, 2005)

Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units. - Jawad Khan; Ranga Vemuri (IPDPS, 2005)

Analog VLSI circuit-level synthesis using multi-placement structures. - Raoul F. Badaoui; Ranga Vemuri (ISCAS (6), 2005)

Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs. - Renqiu Huang; Ranga Vemuri (ISVLSI, 2005)

Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. - Huiying Yang; Anuradha Agarwal; Ranga Vemuri (ISVLSI, 2005)

An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification. - Mengmeng Ding; Ranga Vemuri (VLSI Design, 2005)

On-Line Synthesis for Partially Reconfigurable FPGAs. - Renqiu Huang; Ranga Vemuri (VLSI Design, 2005)

On Physical-Aware Synthesis of Vertically Integrated 3D Systems. - Madhubanti Mukherjee; Ranga Vemuri (VLSI Design, 2005)

Hardware assisted two dimensional ultra fast online placement. - Manish Handa; Ranga Vemuri (Int. J. Embed. Syst., 2005)

optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs. - Balasubramanian Sethuraman; Ranga Vemuri (DATE, 2006)

Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis. - Huiying Yang; Ranga Vemuri (DATE, 2006)

Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip. - Balasubramanian Sethuraman; Ranga Vemuri (FPL, 2006)

Transformation synthesis for data intensive applications to FPGAs. - Renqiu Huang; Ranga Vemuri (ACM Great Lakes Symposium on VLSI, 2006)

Studying a GALS FPGA architecture using a parameterized automatic design flow. - Xin Jia; Ranga Vemuri (ICCAD, 2006)

Exact hierarchical symbolic analysis of large analog networks using a general interconnection template. - Mukesh Ranjan; Ranga Vemuri (ISCAS, 2006)

A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. - Vijay Sundaresan; Ranga Vemuri (ISVLSI, 2006)

Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics. - Amitava Bhaduri; Ranga Vemuri (VLSI Design, 2006)

Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. - Ritochit Chakraborty; Mukesh Ranjan; Ranga Vemuri (VLSI Design, 2006)

Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition. - Mengmeng Ding; Ranga Vemuri (VLSI Design, 2006)

CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture. - Xin Jia; Ranga Vemuri (VLSI Design, 2006)

Hierarchical constraint transformation based on genetic optimization for analog system synthesis. - Nagu R. Dhanwada; Alex Doboli; Adrián Núñez-Aldana; Ranga Vemuri (Integr., 2006)

Energy management for battery-powered reconfigurable computing platforms. - Jawad Khan; Ranga Vemuri (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Power variations of multi-port routers in an application-specific NoC design : A case study. - Balasubramanian Sethuraman; Ranga Vemuri (ICCD, 2007)

A spline based regression technique on interval valued noisy data. - Balaji Kommineni; Shubhankar Basu; Ranga Vemuri (ICMLA, 2007)

GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis. - Angan Das; Ranga Vemuri (ISCAS, 2007)

Multicasting based topology generation and core mapping for a power efficient networks-on-chip. - Balasubramanian Sethuraman; Ranga Vemuri (ISLPED, 2007)

Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. - Shubhankar Basu; Priyanka Thakore; Ranga Vemuri (ISQED, 2007)

Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. - Shubhankar Basu; Ranga Vemuri (ISVLSI, 2007)

An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms. - Angan Das; Ranga Vemuri (ISVLSI, 2007)

Regression based circuit matrix models for accurate performance estimation of analog circuits. - Almitra Pradhan; Ranga Vemuri (VLSI-SoC, 2007)

Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis. - Almitra Pradhan; Ranga Vemuri (VLSI-SoC (Selected Papers), 2007)

Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. - Vijay Sundaresan; Srividhya Rammohan; Ranga Vemuri (VLSI-SoC, 2007)

A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures. - Balasubramanian Sethuraman; Ranga Vemuri (VLSI Design, 2007)

Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis. - Huiying Yang; Ranga Vemuri (VLSI Design, 2007)

Topology synthesis of analog circuits based on adaptively generated building blocks. - Angan Das; Ranga Vemuri (DAC, 2008)

Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches. - Almitra Pradhan; Ranga Vemuri (DATE, 2008)

A Self-learning Optimization Technique for Topology Design of Computer Networks. - Angan Das; Ranga Vemuri (EvoWorkshops, 2008)

A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection. - Almitra Pradhan; Ranga Vemuri (ACM Great Lakes Symposium on VLSI, 2008)

Accurate energy breakeven time estimation for run-time power gating. - Hao Xu 010; Wen-Ben Jone; Ranga Vemuri (ICCAD, 2008)

Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. - Hao Xu 010; Ranga Vemuri; Wen-Ben Jone (ICCD, 2008)

ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework. - Angan Das; Ranga Vemuri (ISCAS, 2008)

Dynamic virtual ground voltage estimation for power gating. - Hao Xu 010; Ranga Vemuri; Wen-Ben Jone (ISLPED, 2008)

Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. - Shubhankar Basu; Balaji Kommineni; Ranga Vemuri (ISQED, 2008)

Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples. - Shubhankar Basu; Balaji Kommineni; Ranga Vemuri (VLSI Design, 2008)

On the Use of Hash Tables for Efficient Analog Circuit Synthesis. - Almitra Pradhan; Ranga Vemuri (VLSI Design, 2008)

Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design. - Srividhya Rammohan; Vijay Sundaresan; Ranga Vemuri (VLSI Design, 2008)

A graph grammar based approach to automated multi-objective analog circuit design. - Angan Das; Ranga Vemuri (DATE, 2009)

Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. - Hao Xu 010; Ranga Vemuri; Wen-Ben Jone (DATE, 2009)

A methodology for application-specific NoC architecture generation in a dynamic task structure environment. - Balasubramanian Sethuraman; Ranga Vemuri (ACM Great Lakes Symposium on VLSI, 2009)

Temporal and spatial idleness exploitation for optimal-grained leakage control. - Hao Xu 010; Ranga Vemuri; Wen-Ben Jone (ICCAD, 2009)

Accurate estimation of vector dependent leakage power in the presence of process variations. - Romana Fernandes; Ranga Vemuri (ICCD, 2009)

Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space. - Shubhankar Basu; Balaji Kommineni; Ranga Vemuri (VLSI Design, 2009)

Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design. - Angan Das; Ranga Vemuri (VLSI Design, 2009)

Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits. - Almitra Pradhan; Ranga Vemuri (VLSI Design, 2009)

Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. - Hao Xu 010; Wen-Ben Jone; Ranga Vemuri (ICCAD, 2010)

Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. - Hao Xu 010; Ranga Vemuri; Wen-Ben Jone (ICCAD, 2010)

A reconfigurable architecture for multicore systems. - Annie Avakian; Jon Nafziger; Amayika Panda; Ranga Vemuri (IPDPS Workshops, 2010)

A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems. - Jon Nafziger; Annie Avakian; Ranga Vemuri (SoCC, 2010)

Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. - Hao Xu 010; Wen-Ben Jone; Ranga Vemuri (VLSI Design, 2010)

Tuning Vth Hopping for Aggressive Runtime Leakage Control. - Hao Xu 010; Wen-Ben Jone; Ranga Vemuri (J. Low Power Electron., 2010)

Configurable workload generators for multicore architectures. - Amayika Panda; Annie Avakian; Ranga Vemuri (SoCC, 2011)

Aggressive Runtime Leakage Control Through Adaptive Light-Weight Vth Hopping With Temperature and Process Variation. - Hao Xu 010; Wen-Ben Jone; Ranga Vemuri (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Dynamic Characteristics of Power Gating During Mode Transition. - Hao Xu 010; Ranga Vemuri; Wen-Ben Jone (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Reconfigurable Multicore Architecture for Dynamic Processor Reallocation. - Annie Avakian; Natwar Agrawal; Ranga Vemuri (ARC, 2012)

SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits. - Lakshmi Narasimhan Ramakrishnan; Manoj Chakkaravarthy; Antarpreet Singh Manchanda; Mike Borowczak; Ranga Vemuri (HOST, 2012)

A Heterogeneous Cache Distribution with Reconfigurable Interconnect. - Aishwariya Pattabiraman; Annie Avakian; Ranga Vemuri (IPDPS Workshops, 2012)

Secure controllers: Requirements of S*FSM. - Mike Borowczak; Ranga Vemuri (MWSCAS, 2013)

Design automation flow for voltage adaptive optimum granularity LITHE for sequential circuits. - Venkat Krishnan Balasubramanian; Hao Xu 010; Ranga Vemuri (SoCC, 2013)

Enabling Side Channel Secure FSMs in the Presence of Low Power Requirements. - Mike Borowczak; Ranga Vemuri (ISVLSI, 2014)

MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETs. - Ramesh Nair; Ranga Vemuri (SoCC, 2014)

A novel simulation based approach for trace signal selection in silicon debug. - Prabanjan Komari; Ranga Vemuri (ICCD, 2016)

Fast Inversions in Small Finite Fields by Using Binary Trees. - Haibo Yi; Shaohua Tang; Ranga Vemuri (Comput. J., 2016)

Effective Signal Restoration in Post-Silicon Validation. - Xiaobang Liu; Ranga Vemuri (ICCD, 2017)

Improving the Security of Split Manufacturing Using a Novel BEOL Signal Selection Method. - Suyuan Chen; Ranga Vemuri (ACM Great Lakes Symposium on VLSI, 2018)

On state encoding against power analysis attacks for finite state controllers. - Richa Agrawal; Ranga Vemuri (HOST, 2018)

Reverse Engineering of Split Manufactured Sequential Circuits Using Satisfiability Checking. - Suyuan Chen; Ranga Vemuri (ICCD, 2018)

Progressive and secure performance unlocking for digital integrated circuits. - Renuka Lokare; Ranga Vemuri (ICCE, 2018)

A secure tunable-precision architecture for image processing applications. - Ankita Manjunath Nayak; Ranga Vemuri (ICCE, 2018)

Detection of Sequential Trojans in Embedded System Designs Without Scan Chains. - Pranav Dharmadhikari; Akhilesh Raju; Ranga Vemuri (ISVLSI, 2018)

Fast Heuristics for Near-Optimal Signal Restoration in Post-Silicon Validation. - Xiaobang Liu; Ranga Vemuri (ISVLSI, 2018)

On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits. - Suyuan Chen; Ranga Vemuri (VLSI-SoC, 2018)

Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation. - Xiaobang Liu; Ranga Vemuri (VLSID, 2018)

Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits. - Suyuan Chen; Ranga Vemuri (HOST, 2019)

Trust in IoT Devices: A Logic Encryption Perspective. - Yasaswy Kasarabada; David M. Luria; Ranga Vemuri (IFIPIoT, 2019)

On SAT-Based Attacks On Encrypted Sequential Logic Circuits. - Yasaswy Kasarabada; Suyuan Chen; Ranga Vemuri (ISQED, 2019)

Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation. - Xiaobang Liu; Ranga Vemuri (ISQED, 2019)

Deep State Encryption for Sequential Logic Circuits. - Yasaswy Kasarabada; Sudheer Ram Thulasi Raman; Ranga Vemuri (ISVLSI, 2019)

Non-Invasive Reverse Engineering of Finite State Machines Using Power Analysis and Boolean Satisfiability. - Harsh Vamja; Richa Agrawal; Ranga Vemuri (MWSCAS, 2019)

A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration. - Richa Agrawal; Mike Borowczak; Ranga Vemuri (VLSID, 2019)

A State Machine Encoding Methodology Against Power Analysis Attacks. - Richa Agrawal; Ranga Vemuri; Mike Borowczak (J. Electron. Test., 2019)

Mitigating information leakage during critical communication using S*FSM. - Mike Borowczak; Ranga Vemuri (IET Comput. Digit. Tech., 2019)

Signal Selection Heuristics for Post-Silicon Validation. - Suprajaa Tummala; Xiaobang Liu; Ranga Vemuri (ISQED, 2020)

SLED: Sequential Logic Encryption Using Dynamic Keys. - Yasaswy Kasarabada; Vaishali Muralidharan; Ranga Vemuri (MWSCAS, 2020)

StateLock: State Transition Based Logic Locking for Sequential Circuits. - Yasaswy Kasarabada; Ranga Vemuri (VLSID, 2020)

Efficient Methods for SoC Trust Validation Using Information Flow Verification. - Khitam M. Alatoun; Shanmukha Murali Achyutha; Ranga Vemuri (ICCD, 2021)

SRTLock: A Sensitivity Resilient Two-Tier Logic Encryption Scheme. - Nikhil Saxena; Ram Venkat Narayanan; Juneet Kumar Meka; Ranga Vemuri (iSES, 2021)

SoC Trust Validation Using Assertion-Based Security Monitors. - Khitam Alatoun; Bharath Shankaranarayanan; Shanmukha Murali Achyutha; Ranga Vemuri (ISQED, 2021)

Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip. - Subashree Raja; Padmaja Bhamidipati; Xiaobang Liu; Ranga Vemuri (ISVLSI, 2021)

Security Analysis of a System-on-Chip Using Assertion-Based Verification. - Padmaja Bhamidipati; Shanmukha Murali Achyutha; Ranga Vemuri (MWSCAS, 2021)

Educating the Next Generation of Cybersecurity Defenders at the University of Cincinnati. - Carla Purdy; John Marty Emmert; Rashmi Jha; Ranga Vemuri (MWSCAS, 2021)

Logic Encryption for Resource Constrained Designs. - David M. Luria; Ranga Vemuri (IEEE Access, 2021)

Encoding of Finite-State Controllers for Graded Security and Power. - Richa Agrawal; Ranga Vemuri (Behavioral Synthesis for Hardware Security, 2022)

S*FSMs for Reduced Information Leakage: Power Side Channel Protection Through Secure Encoding. - Mike Borowczak; Ranga Vemuri (Behavioral Synthesis for Hardware Security, 2022)

Efficient Method for Timing-based Information Flow Verification in Hardware Designs. - Khitam M. Alatoun; Ranga Vemuri (ACM Great Lakes Symposium on VLSI, 2022)

Model Checking Leveraged Error Localization for Complex RTL Designs. - Suriya Srinivasan; Ranga Vemuri (ICCD, 2022)

Analysis of the Satisfiability Attack Against Logic Encryption Using Synthetic Benchmarks. - Juneet Kumar Meka; Shrinidhi Venkatesh; Ranga Vemuri (iSES, 2022)

ISPLock: A Hybrid Internal State Locking Method Using Polymorphic Gates. - Nikhil Saxena; Ranga Vemuri (ISVLSI, 2022)

FPGA Acceleration of a Stochastic Local Search Portfolio Solver for Boolean Satisfiability. - Christopher Chuvalas; Ranga Vemuri (MWSCAS, 2022)

FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth Memory. - Christopher Chuvalas; Ranga Vemuri (VLSI-SoC, 2022)

Attributed Graph Transformation for Generating Synthetic Benchmarks for Hardware Security. - Juneet Kumar Meka; Ranga Vemuri (ISQED, 2023)

Reverse Engineering Word-Level Models from Look-Up Table Netlists. - Ram Venkat Narayanan; Aparajithan Nathamuni Venkatesan; Kishore Pula; Sundarakumar Muthukumaran; Ranga Vemuri (ISQED, 2023)

Reverse Engineering of RTL Controllers from Look-Up Table Netlists. - Sundarakumar Muthukumaran; Aparajithan Nathamuni Venkatesan; Kishore Pula; Ram Venkat Narayanan; Ranga Vemuri; John Marty Emmert (ISVLSI, 2023)

Split Manufacturing Based Secure Hardware Design by BEOL Signal Selection In High Level Synthesis. - Haimanti Chakraborty; Ranga Vemuri (MWSCAS, 2023)

RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks. - Kishore Pula; Aparajithan Nathamuni Venkatesan; Ram Venkat Narayanan; Sundarakumar Muthukumaran; Ranga Vemuri; John Marty Emmert (MWSCAS, 2023)

ASPIRE: An Intermediate Representation for Abstract Security Policies. - Padmaja Bhamidipati; Ranga Vemuri (VLSID, 2023)

Mutation Analysis and Model Checking Guided Test Generation for SoC Run-Time Monitors. - Suriya Srinivasan; Ranga Vemuri (VLSID, 2023)

Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information. - Aparajithan Nathamuni Venkatesan; Ram Venkat Narayanan; Kishore Pula; Sundarakumar Muthukumaran; Ranga Vemuri (VLSID, 2023)

Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption. - Nikhil Saxena; Ranga Vemuri (IEEE Access, 2023)

RTL Interconnect Obfuscation By Polymorphic Switch Boxes For Secure Hardware Generation. - Haimanti Chakraborty; Ranga Vemuri (ISQED, 2024)

QA-NoCs: Quantitative Analysis for Trojan Detection in Network-on-Chips. - Padmaja Bhamidipati; Ranga Vemuri (ISVLSI, 2024)

NoC-Armor: Leveraging Quantitative Analysis for Enhanced Security. - Padmaja Bhamidipati; Ranga Vemuri (MWSCAS, 2024)

Combined Split Manufacturing and Logic Obfuscation Based on Emerging Technologies at High Level for Secure 3D IC Design. - Haimanti Chakraborty; Ranga Vemuri (MWSCAS, 2024)

ACT: Attributed Circuit Transformation System for Synthetic Circuit Generation. - Juneet Kumar Meka; Ranga Vemuri (MWSCAS, 2024)

ROBUST: RTL OBfuscation USing Bi-functional Polymorphic OperaTors. - Haimanti Chakraborty; Ranga Vemuri (VLSID, 2024)

Pattern Based Synthetic Benchmark Generation for Hardware Security Applications. - Juneet Kumar Meka; Satya AmarKant Marupureddy; Ranga Vemuri (VLSID, 2024)

Enhancing Output Corruption Through GSHE Switch Based Logic Encryption. - Nikhil Saxena; Ranga Vemuri (VLSID, 2024)

Trojan Localization Using Information Flow Tracking Properties in SoC Designs. - Suriya Srinivasan; Ranga Vemuri (VLSID, 2024)

Assertion-Based Trojan Localization Using Iterative Path Sensitization. - Suriya Srinivasan; Andrew Jones; Cameron Hingson; Gannon Darrach; Ranga Vemuri (ISQED, 2025)