VESPA: Variability emulation for System-on-Chip performance analysis. - Vivek Joy Kozhikkottu; Rangharajan Venkatesan; Anand Raghunathan; Sujit Dey (DATE, 2011)

MACACO: Modeling and analysis of circuits for approximate computing. - Rangharajan Venkatesan; Amit Agarwal 001; Kaushik Roy 001; Anand Raghunathan (ICCAD, 2011)

Energy efficient many-core processor for recognition and mining using spin-based memory. - Rangharajan Venkatesan; Vinay K. Chippa; Charles Augustine; Kaushik Roy 001; Anand Raghunathan (NANOARCH, 2011)

TapeCache: a high density, energy efficient cache based on domain wall memory. - Rangharajan Venkatesan; Vivek Joy Kozhikkottu; Charles Augustine; Arijit Raychowdhury; Kaushik Roy 001; Anand Raghunathan (ISLPED, 2012)

DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes. - Rangharajan Venkatesan; Mrigank Sharad; Kaushik Roy 001; Anand Raghunathan (DATE, 2013)

Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches. - Mrigank Sharad; Rangharajan Venkatesan; Anand Raghunathan; Kaushik Roy 001 (ISLPED, 2013)

Reading spin-torque memory with spin-torque sensors. - Mrigank Sharad; Rangharajan Venkatesan; Xuanyao Fong; Anand Raghunathan; Kaushik Roy 001 (NANOARCH, 2013)

STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies. - Rangharajan Venkatesan; Shankar Ganesh Ramasubramanian; Swagath Venkataramani; Kaushik Roy 001; Anand Raghunathan (ISCA, 2014)

SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing. - Shankar Ganesh Ramasubramanian; Rangharajan Venkatesan; Mrigank Sharad; Kaushik Roy 001; Anand Raghunathan (ISLPED, 2014)

Computing with Spintronics: Circuits and architectures - Rangharajan Venkatesan (2014)

Asymmetric underlapped FinFET based robust SRAM design at 7nm node. - A. Arun Goud; Rangharajan Venkatesan; Anand Raghunathan; Kaushik Roy 001 (DATE, 2015)

DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes. - Ashish Ranjan 001; Shankar Ganesh Ramasubramanian; Rangharajan Venkatesan; Vijay S. Pai; Kaushik Roy 001; Anand Raghunathan (DATE, 2015)

Spintastic: spin-based stochastic logic for energy-efficient computing. - Rangharajan Venkatesan; Swagath Venkataramani; Xuanyao Fong; Kaushik Roy 001; Anand Raghunathan (DATE, 2015)

Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage. - Rangharajan Venkatesan; Mrigank Sharad; Kaushik Roy 001; Anand Raghunathan (ACM J. Emerg. Technol. Comput. Syst., 2015)

A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications. - Injoon Hong; Jason Clemons; Rangharajan Venkatesan; Iuri Frosio; Brucek Khailany; Stephen W. Keckler (DAC, 2016)

Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes. - A. Arun Goud; Rangharajan Venkatesan; Anand Raghunathan; Kaushik Roy 001 (ACM J. Emerg. Technol. Comput. Syst., 2016)

Spin-Transfer Torque Memories: Devices, Circuits, and Systems. - Xuanyao Fong; Yusung Kim 002; Rangharajan Venkatesan; Sri Harsha Choday; Anand Raghunathan; Kaushik Roy 001 (Proc. IEEE, 2016)

Cache Design with Domain Wall Memory. - Rangharajan Venkatesan; Vivek Joy Kozhikkottu; Mrigank Sharad; Charles Augustine; Arijit Raychowdhury; Kaushik Roy 001; Anand Raghunathan (IEEE Trans. Computers, 2016)

Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches. - Xuanyao Fong; Rangharajan Venkatesan; Dongsoo Lee; Anand Raghunathan; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Emulation-Based Analysis of System-on-Chip Performance Under Variations. - Vivek Joy Kozhikkottu; Rangharajan Venkatesan; Anand Raghunathan; Sujit Dey (IEEE Trans. Very Large Scale Integr. Syst., 2016)

STAxCache: An approximate, energy efficient STT-MRAM cache. - Ashish Ranjan 001; Swagath Venkataramani; Zoha Pajouhi; Rangharajan Venkatesan; Kaushik Roy 001; Anand Raghunathan (DATE, 2017)

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. - Angshuman Parashar; Minsoo Rhu; Anurag Mukkara; Antonio Puglielli; Rangharajan Venkatesan; Brucek Khailany; Joel S. Emer; Stephen W. Keckler; William J. Dally (ISCA, 2017)

A modular digital VLSI flow for high-productivity SoC design. - Brucek Khailany; Evgeni Khmer; Rangharajan Venkatesan; Jason Clemons; Joel S. Emer; Matthew Fojtik; Alicia Klinefelter; Michael Pellauer; Nathaniel Ross Pinckney; Yakun Sophia Shao; Shreesha Srinath; Christopher Torng; et al. (DAC, 2018)

Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. - Michael Pellauer; Yakun Sophia Shao; Jason Clemons; Neal Clayton Crago; Kartik Hegde; Rangharajan Venkatesan; Stephen W. Keckler; Christopher W. Fletcher; Joel S. Emer (ASPLOS, 2019)

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. - Angad S. Rekhi; Brian Zimmer; Nikola Nedovic; Ningxi Liu; Rangharajan Venkatesan; Miaorong Wang; Brucek Khailany; William J. Dally; C. Thomas Gray (DAC, 2019)

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. - Rangharajan Venkatesan; Yakun Sophia Shao; Brian Zimmer; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Hot Chips Symposium, 2019)

MAGNet: A Modular Accelerator Generator for Neural Networks. - Rangharajan Venkatesan; Yakun Sophia Shao; Miaorong Wang; Jason Clemons; Steve Dai; Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Yanqing Zhang 002; Brian Zimmer; et al. (ICCAD, 2019)

Timeloop: A Systematic Approach to DNN Accelerator Evaluation. - Angshuman Parashar; Priyanka Raina; Yakun Sophia Shao; Yu-Hsin Chen; Victor A. Ying; Anurag Mukkara; Rangharajan Venkatesan; Brucek Khailany; Stephen W. Keckler; Joel S. Emer (ISPASS, 2019)

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (MICRO, 2019)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (VLSI Circuits, 2019)

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (IEEE J. Solid State Circuits, 2020)

Accelerating Chip Design With Machine Learning. - Brucek Khailany; Haoxing Ren; Steve Dai; Saad Godil; Ben Keller; Robert Kirby 001; Alicia Klinefelter; Rangharajan Venkatesan; Yanqing Zhang 002; Bryan Catanzaro; William J. Dally (IEEE Micro, 2020)

Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. - Jacob R. Stevens; Rangharajan Venkatesan; Steve Dai; Brucek Khailany; Anand Raghunathan (DAC, 2021)

IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs. - Nathaniel Ross Pinckney; Rangharajan Venkatesan; Ben Keller; Brucek Khailany (ICCAD, 2021)

Session 3 Overview: Highlighted Chip Releases: Modern Digital SoCs Invited Papers. - Thomas Burd; Rangharajan Venkatesan; Dennis Sylvester (ISSCC, 2021)

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. - Steve Dai; Rangharajan Venkatesan; Mark Ren; Brian Zimmer; William J. Dally; Brucek Khailany (MLSys, 2021)

Simba: scaling deep-learning inference with chiplet-based architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Commun. ACM, 2021)

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. - Steve Dai; Rangharajan Venkatesan; Haoxing Ren; Brian Zimmer; William J. Dally; Brucek Khailany (CoRR, 2021)

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking. - Steve Dai; Alicia Klinefelter; Haoxing Ren; Rangharajan Venkatesan; Ben Keller; Nathaniel Ross Pinckney; Brucek Khailany (CoRR, 2021)

Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update. - Jiawei Zhao; Steve Dai; Rangharajan Venkatesan; Ming-Yu Liu 001; Brucek Khailany; Bill Dally; Anima Anandkumar (CoRR, 2021)

Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. - Charbel Sakr; Steve Dai; Rangharajan Venkatesan; Brian Zimmer; William J. Dally; Brucek Khailany (ICML, 2022)

A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. - Ben Keller; Rangharajan Venkatesan; Steve Dai; Stephen G. Tell; Brian Zimmer; William J. Dally; C. Thomas Gray; Brucek Khailany (VLSI Technology and Circuits, 2022)

Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications. - Kavya Sreedhar; Jason Clemons; Rangharajan Venkatesan; Stephen W. Keckler; Mark Horowitz (CoRR, 2022)

Fair and Comprehensive Benchmarking of Machine Learning Processing Chips. - Geoffrey W. Burr; Sukhwan Lim; Boris Murmann; Rangharajan Venkatesan; Marian Verhelst (IEEE Des. Test, 2022)

LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update. - Jiawei Zhao; Steve Dai; Rangharajan Venkatesan; Brian Zimmer; Mustafa Fayez Ali; Ming-Yu Liu 001; Brucek Khailany; William J. Dally; Anima Anandkumar (IEEE Trans. Computers, 2022)

Efficient Transformer Inference with Statically Structured Sparse Attention. - Steve Dai; Hasan Genc; Rangharajan Venkatesan; Brucek Khailany (DAC, 2023)

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. - Ben Keller; Rangharajan Venkatesan; Steve Dai; Stephen G. Tell; Brian Zimmer; Charbel Sakr; William J. Dally; C. Thomas Gray; Brucek Khailany (IEEE J. Solid State Circuits, 2023)

Vision Transformer Computation and Resilience for Dynamic Inference. - Kavya Sreedhar; Jason Clemons; Rangharajan Venkatesan; Stephen W. Keckler; Mark Horowitz (ISPASS, 2024)

SQ-DM: Accelerating Diffusion Models with Aggressive Quantization and Temporal Sparsity. - Zichen Fan; Steve Dai; Rangharajan Venkatesan; Dennis Sylvester; Brucek Khailany (CoRR, 2025)

FGMP: Fine-Grained Mixed-Precision Weight and Activation Quantization for Hardware-Accelerated LLM Inference. - Coleman Hooper; Charbel Sakr; Ben Keller; Rangharajan Venkatesan; Kurt Keutzer; Yakun Sophia Shao; Brucek Khailany (CoRR, 2025)