Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model. - Rani S. Ghaida; Payman Zarkesh-Ha (DFT, 2007)

A framework for early and systematic evaluation of design rules. - Rani S. Ghaida; Puneet Gupta 001 (ICCAD, 2009)

A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects. - Rani S. Ghaida; Payman Zarkesh-Ha (J. Electron. Test., 2009)

Electrical Modeling of Lithographic Imperfections. - Tuck-Boon Chan; Rani S. Ghaida; Puneet Gupta 001 (VLSI Design, 2010)

A framework for double patterning-enabled design. - Rani S. Ghaida; Kanak B. Agarwal; Sani R. Nassif; Xin Yuan; Lars Liebmann; Puneet Gupta 001 (ICCAD, 2011)

A methodology for the early exploration of design rules for multiple-patterning technologies. - Rani S. Ghaida; Tanaya Sahu; Parag Kulkarni; Puneet Gupta 001 (ICCAD, 2012)

O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction. - Rani S. Ghaida; Kanak B. Agarwal; Sani R. Nassif; Xin Yuan; Lars W. Liebmann; Puneet Gupta 001 (ICICDT, 2012)

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies. - Rani S. Ghaida; Puneet Gupta 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies - Rani S. Ghaida (2012)

Role of design in multiple patterning: technology development, design enablement and process control. - Rani S. Ghaida; Puneet Gupta 001 (DATE, 2013)

Layout Decomposition and Legalization for Double-Patterning Technology. - Rani S. Ghaida; Kanak B. Agarwal; Sani R. Nassif; Xin Yuan; Lars Liebmann; Puneet Gupta 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Comprehensive die-level assessment of design rules and layouts. - Rani S. Ghaida; Yasmine Badr; Mukul Gupta; Ning Jin; Puneet Gupta 001 (ASP-DAC, 2014)

Pattern-restricted design at 10nm and beyond. - Rani S. Ghaida; Yasmine Badr; Puneet Gupta 001 (ICCD, 2014)