A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process. - Krishnaswamy Nagaraj; David A. Martin; Mark A. Wolfe; Ranjan Chattopadhyay; Shanthi Pavan; Jason Cancio; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 2000)

A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation. - Gennady Feygin; Krishnaswamy Nagaraj; Ranjan Chattopadhyay; R. Herrera; I. Papantonopoulos; David A. Martin; P. Wu; Shanthi Pavan (CICC, 2001)