Performance analysis of a multiprocessor machine based on data flow principles. - Ranjani Narayan; V. Rajaraman (Microprocessing and Microprogramming, 1990)

A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. - S. K. Nandy 001; Ranjani Narayan; V. Visvanathan; P. Sadayappan; Prashant S. Chauhan (ICPP (3), 1993)

A Framework for QoS Adaptive Grid Meta Scheduling. - K. C. Nainwal; J. Lakshmi; S. K. Nandy 001; Ranjani Narayan; Keshavan Varadarajan (DEXA Workshops, 2005)

Framework for Enabling Highly Available Distributed Applications for Utility Computing. - J. Lakshmi; S. K. Nandy 001; Ranjani Narayan; Keshavan Varadarajan (ISPA, 2006)

REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. - A. N. Satrawala; Keshavan Varadarajan; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (FPL, 2007)

Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. - Adarsha Rao; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (ASAP, 2008)

Synthesis of application accelerators on Runtime Reconfigurable Hardware. - Mythri Alle; Keshavan Varadarajan; Ramesh C. Ramesh; Joseph Nimmy; Alexander Fell; Adarsha Rao; S. K. Nandy 001; Ranjani Narayan (ASAP, 2008)

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. - Joseph Nimmy; C. Ramesh Reddy; Keshavan Varadarajan; Mythri Alle; Alexander Fell; S. K. Nandy 001; Ranjani Narayan (ASAP, 2008)

Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. - Mythri Alle; Keshavan Varadarajan; Alexander Fell; S. K. Nandy 001; Ranjani Narayan (ARC, 2009)

An Input Triggered Polymorphic ASIC for H.264 Decoding. - Adarsha Rao; Mythri Alle; Sainath V; Reyaz Shaik; Rajashekhar Chowhan; Sreeramula Sankaraiah; Sravanthi Mantha; S. K. Nandy 001; Ranjani Narayan (ASAP, 2009)

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. - Alexander Fell; Mythri Alle; Keshavan Varadarajan; Prasenjit Biswas; Saptarsi Das; Jugantor Chetia; S. K. Nandy 001; Ranjani Narayan (CASES, 2009)

Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. - Alexander Fell; Prasenjit Biswas; Jugantor Chetia; S. K. Nandy 001; Ranjani Narayan (SoCC, 2009)

REDEFINE: Runtime reconfigurable polymorphic ASIC. - Mythri Alle; Keshavan Varadarajan; Alexander Fell; C. Ramesh Reddy; Joseph Nimmy; Saptarsi Das; Prasenjit Biswas; Jugantor Chetia; Adarsha Rao; S. K. Nandy 001; Ranjani Narayan (ACM Trans. Embed. Comput. Syst., 2009)

Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. - Ratna Krishnamoorthy; Keshavan Varadarajan; Ganesh Garga; Mythri Alle; S. K. Nandy 001; Ranjani Narayan; Masahiro Fujita (CASES, 2010)

Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. - Prasenjit Biswas; Pramod P. Udupa; Rajdeep Mondal; Keshavan Varadarajan; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (ISVLSI, 2010)

Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. - Prasenjit Biswas; Keshavan Varadarajan; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (ICSAMOS, 2010)

Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture. - N. Thambi Prashank; M. Prasadarao; Avinaba Dutta; Keshavan Varadarajan; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (ICSAMOS, 2010)

Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. - Ratna Krishnamoorthy; Keshavan Varadarajan; Masahiro Fujita; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (ARC, 2011)

Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields. - Saptarsi Das; Ranjani Narayan; Soumitra Kumar Nandy (ICETE (Selected Papers), 2011)

A Method for Flexible Reduction over Binary Fields using a Field Multiplier. - Saptarsi Das; Keshavan Varadarajan; Ganesh Garga; Rajdeep Mondal; Ranjani Narayan; S. K. Nandy 001 (SECRYPT, 2011)

Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture. - Ratna Krishnamoorthy; Saptarsi Das; Keshavan Varadarajan; Mythri Alle; Masahiro Fujita; Soumitra Kumar Nandy; Ranjani Narayan (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. - S. Kala; Nalesh Sivanandan; Arka Maity; S. K. Nandy 001; Ranjani Narayan (ISCAS, 2013)

Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. - S. Kala; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (ISED, 2014)

Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath. - Kavitha T. Madhu; Saptarsi Das; Madhava Krishna C; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (ICSAMOS, 2014)

Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs. - Mahesh Mahadurkar; Farhad Merchant; Arka Maity; Kapil Vatwani; Ishan Munje; Nandhini Gopalan; S. K. Nandy 001; Ranjani Narayan (ICSAMOS, 2014)

Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). - Farhad Merchant; Anupam Chattopadhyay; Ganesh Garga; S. K. Nandy 001; Ranjani Narayan; Nandhini Gopalan (VLSID, 2014)

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. - Saptarsi Das; Kavitha T. Madhu; Madhav Krishna; Nalesh Sivanandan; Farhad Merchant; Santhi Natarajan; Ipsita Biswas; Adithya Pulli; S. K. Nandy 001; Ranjani Narayan (J. Syst. Archit., 2014)

Compiling HPC Kernels for the REDEFINE CGRA. - Kavitha T. Madhu; Saptarsi Das; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (HPCC/CSS/ICESS, 2015)

Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. - Nalesh Sivanandan; Kavitha T. Madhu; Saptarsi Das; S. K. Nandy 001; Ranjani Narayan (iNIS, 2015)

A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address. - Alexander Fell; S. K. Nandy 001; Ranjani Narayan (SoCC, 2015)

Hardware Solution for Real-Time Face Recognition. - Gopinath Mahale; Hamsika Mahale; Arnav Goel; S. K. Nandy 001; S. Bhattacharya; Ranjani Narayan (VLSID, 2015)

Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. - Farhad Merchant; Arka Maity; Mahesh Mahadurkar; Kapil Vatwani; Ishan Munje; Madhava Krishna C; Nalesh Sivanandan; Nandhini Gopalan; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (VLSID, 2015)

A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks. - Mahnaz Mohammadi; Nitin Satpute; Rohit Ronge; Jayesh R. Chandiramani; S. K. Nandy 001; Aamir Raihan; Tanmay Verma; Ranjani Narayan; Sukumar Bhattacharya (VLSID, 2015)

Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat. - Arnab Kumar Biswas; S. K. Nandy 001; Ranjani Narayan (Circuits Syst. Signal Process., 2015)

Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. - S. Kala; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (J. Low Power Electron., 2015)

Flexible resource allocation and management for application graphs on ReNÉ MPSoC. - Kavitha T. Madhu; Anuj Rao; Saptarsi Das; Krishna C. Madhava; S. K. Nandy 001; Ranjani Narayan (PARMA-DITAM@HiPEAC, 2016)

RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. - Saptarsi Das; Nalesh Sivanandan; Kavitha T. Madhu; Soumitra Kumar Nandy; Ranjani Narayan (VLSID, 2016)

VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks. - Gopinath Mahale; Soumitra Kumar Nandy; Eshan Bhatia; S. K. Nandy 001; Ranjani Narayan (VLSID, 2016)

Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic. - Farhad Merchant; Nimash Choudhary; S. K. Nandy 001; Ranjani Narayan (VLSID, 2016)

Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (VLSID, 2016)

Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (CoRR, 2016)

REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores. - Gopinath Mahale; Hamsika Mahale; S. K. Nandy 001; Ranjani Narayan (IEEE Trans. Parallel Distributed Syst., 2016)

REDEFINE®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress). - Kavitha T. Madhu; Tarun Singla; S. K. Nandy 001; Ranjani Narayan; François Neumann; Philippe Baufreton (CASES, 2017)

Energy aware synthesis of application kernels through composition of data-paths on a CGRA. - Nalesh Sivanandan; Kavitha T. Madhu; Saptarsi Das; S. K. Nandy 001; Ranjani Narayan (Integr., 2017)

Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. - Farhad Merchant; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (Parallel Process. Lett., 2017)

Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (ARC, 2018)

Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan; Rainer Leupers (CoRR, 2018)

Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (IEEE Trans. Parallel Distributed Syst., 2018)

A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan; Rainer Leupers (VLSID, 2019)

Applying Modified Householder Transform to Kalman Filter. - Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan; Rainer Leupers (VLSID, 2019)