A Strategy for Soft Error Reduction in Multi Core Designs. - Ransford Hyman Jr.; Koustav Bhattacharya; N. Ranganathan (ISCAS, 2009)

Redundancy Mining for Soft Error Detection in Multicore Processors. - Ransford Hyman Jr.; Koustav Bhattacharya; Nagarajan Ranganathan (IEEE Trans. Computers, 2011)

Dynamic clock stretching for variation compensation in VLSI circuit design. - Venkataraman Mahalingam; Nagarajan Ranganathan; Ransford Hyman Jr. (ACM J. Emerg. Technol. Comput. Syst., 2012)

A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering. - Ransford Hyman Jr.; Nagarajan Ranganathan; Thomas Bingel; Deanne Tran Vo (IEEE Trans. Very Large Scale Integr. Syst., 2013)