Universal test generation using fault tuples. - Rao Desineni; Kumar N. Dwarakanath; Ronald D. Blanton (ITC, 2000)

Fault Tuples in Diagnosis of Deep-Submicron Circuits. - Ronald D. Blanton; John T. Chen; Rao Desineni; Kumar N. Dwarakanath; Wojciech Maly; Thomas J. Vogels (ITC, 2002)

Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. - Thomas J. Vogels; Thomas Zanon; Rao Desineni; R. D. (Shawn) Blanton; Wojciech Maly; Jason G. Brown; Jeffrey E. Nelson; Y. Fei; X. Huang; Padmini Gopalakrishnan; Mahim Mishra; Vyacheslav Rovner; et al. (ITC, 2004)

Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction. - Rao Desineni; R. D. (Shawn) Blanton (VTS, 2005)

Multiple-detect ATPG based on physical neighborhoods. - Jeffrey E. Nelson; Jason G. Brown; Rao Desineni; R. D. (Shawn) Blanton (DAC, 2006)

Extraction of defect density and size distributions from wafer sort test results. - Jeffrey E. Nelson; Thomas Zanon; Rao Desineni; Jason G. Brown; N. Patil; Wojciech Maly; R. D. (Shawn) Blanton (DATE, 2006)

A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior. - Rao Desineni; Osei Poku; Ronald D. Blanton (ITC, 2006)

Defect Modeling Using Fault Tuples. - Ronald D. Blanton; Kumar N. Dwarakanath; Rao Desineni (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Hard to find, easy to find systematics; just find them. - Rao Desineni; Leah Pastel; Maroun Kassab; Robert Redburn (ITC, 2010)

Deriving Feature Fail Rate from Silicon Volume Diagnostics Data. - Shobhit Malik; Thomas Herrmann; Sriram Madhavan; Rao Desineni; Chris Schuermyer; Geir Eide (IEEE Des. Test, 2013)

Pylon: Towards an integrated customizable volume diagnosis infrastructure. - Yan Pan; Rao Desineni; Kannan Sekar; Atul Chittora; Sherwin Fernandes; Neerja Bawaskar; John M. Carulli (ITC, 2016)