A high-speed 128-kb MRAM core for future universal memory applications. - John K. DeBrosse; Dietmar Gogl; Alexander Bette; Heinz Hoenigschmid; Raphael Robertazzi; Christian Arndt; Daniel Braun 011; D. Casarotto; Robert Havreluk; Stefan Lammers; Werner Obermaier; William R. Reohr; et al. (IEEE J. Solid State Circuits, 2004)

A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors. - Pong-Fei Lu; Nianzheng Cao; Leon J. Sigal; Pieter Woltgens; Raphael Robertazzi; David F. Heidel (ISLPED, 2006)

New tools and methodology for advanced parametric and defect structure test. - Raphael Robertazzi; Louis Medina; Ernesto Shiling; Garry Moore; Ronald Geiger; Jiun-Hsin Liao; John Williamson (ITC, 2010)

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. - Zeynep Toprak Deniz; Michael A. Sperling; John F. Bulzacchelli; Gregory S. Still; Ryan Kruse; Seongwon Kim; David Boerstler; Tilman Gloekler; Raphael Robertazzi; Kevin Stawiasz; Tim Diemoz; George English; et al. (ISSCC, 2014)

Analytical MRAM test. - Raphael Robertazzi; Janusz Nowak; Jonathan Sun (ITC, 2014)

Analyzing path delays for accelerated testing of logic chips. - Emily Ray; Barry P. Linder; Raphael Robertazzi; Kevin Stawiasz; Alan J. Weger; Emmanuel Yashchin; James H. Stathis; Peilin Song (IRPS, 2015)

TSV/FET proximity study using dense addressable transistor arrays. - Raphael Robertazzi; Kanak Agarwal 001; Bucknell Webb; Christy Tyberg (IRPS, 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)

Thermal analysis of multi-layer functional 3D logic stacks. - Michael Scheuermann; Shurong Tian; Raphael Robertazzi; Matthew R. Wordeman; C. Bergeron; H. Jacobson; Phillip J. Restle; Joel Silberman; Christy Tyberg (3DIC, 2016)

Analytical test of 3D integrated circuits. - Raphael Robertazzi; Micheal Scheurman; Matt Wordeman; Shurong Tian; Christy Tyberg (ITC, 2017)

A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation. - Kevin Tien; Ken Inoue; Scott Lekuch; David J. Frank; Sudipto Chakraborty; Pat Rosno; Thomas Fox; Mark Yeck; Joseph A. Glick; Raphael Robertazzi; Ray Richetta; John F. Bulzacchelli; et al. (DATE, 2022)

A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology. - David J. Frank; Sudipto Chakraborty; Kevin Tien; Pat Rosno; Thomas Fox; Mark Yeck; Joseph A. Glick; Raphael Robertazzi; Ray Richetta; John F. Bulzacchelli; Daniel Ramirez; Dereje Yilma; et al. (ISSCC, 2022)

A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology. - Sudipto Chakraborty; David J. Frank; Kevin Tien; Pat Rosno; Mark Yeck; Joseph A. Glick; Raphael Robertazzi; Ray Richetta; John F. Bulzacchelli; Devin Underwood; Daniel Ramirez; Dereje Yilma; et al. (IEEE J. Solid State Circuits, 2022)

Low power cryogenic RF ASICs for quantum computing. - David J. Frank; Sudipto Chakraborty; Kevin Tien; Pat Rosno; Mark Yeck; Joseph A. Glick; Raphael Robertazzi; Ray Richetta; John F. Bulzacchelli; Daniel Ramirez; Dereje Yilma; Andrew Davies; et al. (CICC, 2023)

Characterization of 14nm CMOS Technology At Cryogenic Temperatures Using Dense Addressable Arrays. - Raphael Robertazzi; David J. Frank; Kevin Tien; John Timmerwilke; Peilin Song; Daniel J. Friedman (VTS, 2024)

Cryogenic CMOS Circuits for Future Scaled Quantum Computing Systems: Challenges and Solutions. - Bodhisatwa Sadhu; Kevin Tien; Sudipto Chakraborty; David J. Frank; Pat Rosno; Daniel Moertl; Mark Yeck; John F. Bulzacchelli; Daniil Frolov; Devin Underwood; Ken Inoue; Christian W. Baks; et al. (CICC, 2025)