Design of FPGA interconnect for multilevel metalization. - Raphael Rubin; André DeHon (FPGA, 2003)

Design of FPGA interconnect for multilevel metallization. - André DeHon; Raphael Rubin (IEEE Trans. Very Large Scale Integr. Syst., 2004)

GraphStep: A System Architecture for Sparse-Graph Algorithms. - Michael DeLorimier; Nachiket Kapre; Nikil Mehta; Dominic Rizzo; Ian Eslick; Raphael Rubin; Tomás E. Uribe; Thomas F. Knight Jr.; André DeHon (FCCM, 2006)

Packet Switched vs. Time Multiplexed FPGA Overlay Networks. - Nachiket Kapre; Nikil Mehta; Michael DeLorimier; Raphael Rubin; Henry Barnor; Michael J. Wilson; Michael G. Wrighton; André DeHon (FCCM, 2006)

3D Nanowire-Based Programmable Logic. - Benjamin Gojman; Raphael Rubin; Concetta Pilotto; André DeHon; Tetsufumi Tanamoto (Nano-Net, 2006)

Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging. - Benjamin Gojman; Nikil Mehta; Raphael Rubin; André DeHon (Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011)

Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder. - Raphael Rubin; André DeHon (FPGA, 2011)

Choose-your-own-adventure routing: Lightweight load-time defect avoidance. - Raphael Rubin; André DeHon (ACM Trans. Reconfigurable Technol. Syst., 2011)

Limit study of energy & delay benefits of component-specific routing. - Nikil Mehta; Raphael Rubin; André DeHon (FPGA, 2012)

PUMP: a programmable unit for metadata processing. - Udit Dhawan; Nikos Vasilakis; Raphael Rubin; Silviu Chiricescu; Jonathan M. Smith; Thomas F. Knight Jr.; Benjamin C. Pierce; André DeHon (HASP@ISCA, 2014)

Architectural Support for Software-Defined Metadata Processing. - Udit Dhawan; Catalin Hritcu; Raphael Rubin; Nikos Vasilakis; Silviu Chiricescu; Jonathan M. Smith; Thomas F. Knight Jr.; Benjamin C. Pierce; André DeHon (ASPLOS, 2015)

Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement. - Timothy A. Linscott; Benjamin Gojman; Raphael Rubin; André DeHon (FPGA, 2016)

Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. - Hans Giesen; Raphael Rubin; Benjamin Gojman; André DeHon (FPGA, 2017)

Self-Adaptive Timing Repair. - Hans Giesen; Raphael Rubin; Benjamin Gojman; André DeHon (IEEE Des. Test, 2017)

Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). - Hans Giesen; Benjamin Gojman; Raphael Rubin; Ji Kim; André DeHon (ACM Trans. Reconfigurable Technol. Syst., 2018)

Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks. - Yuanlong Xiao; Dongjoon Park; Andrew Butt; Hans Giesen; Zhaoyang Han; Rui Ding; Nevo Magnezi; Raphael Rubin; André DeHon (FPT, 2019)