Compressing Variable-Length Instruction Traces. - Raphael Moreira Zinsly; Sandro Rigo; Edson Borin (WSCAD-SSC, 2012)

Employing Simulation to Facilitate the Design of Dynamic Code Generators. - Vanderson Martins do Rosario; Raphael Moreira Zinsly; Sandro Rigo; Edson Borin (CoRR, 2020)

Employing Simulation to Facilitate the Design of Dynamic Binary Translators. - Vanderson Martins do Rosario; Raphael Zinsly; Sandro Rigo; Edson Borin (SBAC-PAD, 2021)