On mismatch in the deep sub-micron era - from physics to circuits. - Rasit Onur Topaloglu; Alex Orailoglu (ASP-DAC, 2004)

Forward discrete probability propagation method for device performance characterization under process variations. - Rasit Onur Topaloglu; Alex Orailoglu (ASP-DAC, 2005)

A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs. - Rasit Onur Topaloglu; Alex Orailoglu (DAC, 2005)

Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction. - Rasit Onur Topaloglu; Andrew B. Kahng (ICCD, 2006)

Monte Carlo-Alternative Probabilistic Simulations for Analog Systems. - Rasit Onur Topaloglu (ISQED, 2006)

Generation of design guarantees for interconnect matching. - Andrew B. Kahng; Rasit Onur Topaloglu (SLIP, 2006)

Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System Simulations. - Rasit Onur Topaloglu (VTS, 2006)

Standard Cell and Custom Circuit Optimization using Dummy Diffusions through STI Width Stress Effect Utilization. - Rasit Onur Topaloglu (CICC, 2007)

Exploiting STI stress for performance. - Andrew B. Kahng; Puneet Sharma; Rasit Onur Topaloglu (ICCAD, 2007)

A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances. - Andrew B. Kahng; Rasit Onur Topaloglu (ISQED, 2007)

Energy-Minimization Model for Fill Synthesis. - Rasit Onur Topaloglu (ISQED, 2007)

Process Variation-Aware Multiple-Fault Diagnosis of Thermometer-Coded Current-Steering DACs. - Rasit Onur Topaloglu (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics. - Rasit Onur Topaloglu (ISQED, 2008)

Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion. - Andrew B. Kahng; Puneet Sharma; Rasit Onur Topaloglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Characterization, modeling and optimization of fills and stress in semiconductor integrated circuits. - Rasit Onur Topaloglu (2008)

CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design. - Akif Sultan; John Faricelli; Sushant Suryagandh; Hans vanMeer; Kaveri Mathur; James Pattison; Sean Hannon; Greg Constant; Kalyana Kumar; Kevin Carrejo; Joe Meier; Rasit Onur Topaloglu; et al. (ISQED, 2009)

Is overlay error more important than interconnect variations in double patterning? - Kwangok Jeong; Andrew B. Kahng; Rasit Onur Topaloglu (SLIP, 2009)

Assessing chip-level impact of double patterning lithography. - Kwangok Jeong; Andrew B. Kahng; Rasit Onur Topaloglu (ISQED, 2010)

3-2-1 contact: an experimental approach to the analysisof contacts in 45 nm and below. - Rasit Onur Topaloglu (SLIP, 2010)

Applications driving 3D integration and corresponding manufacturing challenges. - Rasit Onur Topaloglu (DAC, 2011)

Self-aligned double patterning decomposition for overlay minimization and hot spot detection. - Hongbo Zhang 001; Yuelin Du; Martin D. F. Wong; Rasit Onur Topaloglu (DAC, 2011)

GPU programming for EDA with OpenCL. - Rasit Onur Topaloglu; Benedict R. Gaster (ICCAD, 2011)

TSV density-driven global placement for 3D stacked ICs. - Dae Hyun Kim 004; Rasit Onur Topaloglu; Sung Kyu Lim (ISOCC, 2011)

Fast variational static IR-drop analysis on the graphical processing unit. - Rasit Onur Topaloglu (ISQED, 2011)

Device and circuit implications of double-patterning - A designer's perspective. - Rasit Onur Topaloglu (ISQED, 2011)

Block-level 3D IC design with through-silicon-via planning. - Dae Hyun Kim 004; Rasit Onur Topaloglu; Sung Kyu Lim (ASP-DAC, 2012)

Efficient pattern relocation for EUV blank defect mitigation. - Hongbo Zhang 001; Yuelin Du; Martin D. F. Wong; Rasit Onur Topaloglu (ASP-DAC, 2012)

Design with FinFETs: design rules, patterns, and variability. - Rasit Onur Topaloglu (ICCAD, 2013)

Welcome to ISQED 2013. - Mark M. Budnik; Rasit Onur Topaloglu; Pallab Chatterjee; Keith A. Bowman; Kamesh V. Gadepally; Paul Wesling; Syed M. Alam; Rajiv V. Joshi (ISQED, 2013)

Chip-scale physical interconnect models (Tutorial). - Rasit Onur Topaloglu (SLIP, 2013)

Design and technology co-optimization near single-digit nodes. - Lars W. Liebmann; Rasit Onur Topaloglu (ICCAD, 2014)

ICCAD-2014 CAD contest in design for manufacturability flow for advanced semiconductor nodes and benchmark suite. - Rasit Onur Topaloglu (ICCAD, 2014)

Guest Editorial Special Section on Optical Interconnects. - Rasit Onur Topaloglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

ICCAD-2016 CAD contest in pattern classification for integrated circuit design space analysis and benchmark suite. - Rasit Onur Topaloglu (ICCAD, 2016)

Editorial for JETC Special Issue on Alternative Computing Systems. - Rasit Onur Topaloglu; Naveen Verma (ACM J. Emerg. Technol. Comput. Syst., 2017)

MapReduce-based pattern classification for design space analysis. - Yan-Shiun Wu; Hong-Yan Su; Yi-Hsiang Chang; Rasit Onur Topaloglu; Yih-Lang Li (VLSI-DAT, 2018)

Editorial for TODAES Special Issue on Internet of Things System Performance, Reliability, and Security. - Rasit Onur Topaloglu; Farinaz Koushanfar (ACM Trans. Design Autom. Electr. Syst., 2018)

Explainable DRC Hotspot Prediction with Random Forest and SHAP Tree Explainer. - Wei Zeng 015; Azadeh Davoodi; Rasit Onur Topaloglu (DATE, 2020)

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. - Shubham Rai; Walter Lau Neto; Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita; Guilherme B. Manske; Matheus F. Pontes; Leomar S. da Rosa; Marilton S. de Aguiar; Paulo F. Butzen; et al. (DATE, 2021)

A Survey and Tutorial on Security and Resilience of Quantum Computing. - Abdullah Ash-Saki; Mahabubul Alam; Koustubh Phalak; Aakarshitha Suresh; Rasit Onur Topaloglu; Swaroop Ghosh (ETS, 2021)

Sampling-Based Approximate Logic Synthesis: An Explainable Machine Learning Approach. - Wei Zeng 015; Azadeh Davoodi; Rasit Onur Topaloglu (ICCAD, 2021)

Quantum-Classical Hybrid Machine Learning for Image Classification (ICCAD Special Session Paper). - Mahabubul Alam; Satwik Kundu; Rasit Onur Topaloglu; Swaroop Ghosh (ICCAD, 2021)

Split Compilation for Security of Quantum Circuits. - Abdullah Ash-Saki; Aakarshitha Suresh; Rasit Onur Topaloglu; Swaroop Ghosh (ICCAD, 2021)

Lorax: Machine Learning-Based Oracle Reconstruction With Minimal I/O Patterns. - Wei Zeng 015; Azadeh Davoodi; Rasit Onur Topaloglu (ISVLSI, 2021)

Short Paper: A Quantum Circuit Obfuscation Methodology for Security and Privacy. - Aakarshitha Suresh; Abdullah Ash-Saki; Mahababul Alam; Rasit Onur Topaloglu; Swaroop Ghosh (HASP@MICRO, 2021)

Quantum Generative Models for Small Molecule Drug Discovery. - Junde Li; Rasit Onur Topaloglu; Swaroop Ghosh (CoRR, 2021)

Quantum PUF for Security and Trust in Quantum Computing. - Koustubh Phalak; Abdullah Ash-Saki; Mahabubul Alam; Rasit Onur Topaloglu; Swaroop Ghosh (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Muzzle the Shuttle: Efficient Compilation for Multi-Trap Trapped-Ion Quantum Computers. - Abdullah Ash-Saki; Rasit Onur Topaloglu; Swaroop Ghosh (DATE, 2022)

A Shuttle-Efficient Qubit Mapper for Trapped-Ion Quantum Computers. - Suryansh Upadhyay; Abdullah Ash-Saki; Rasit Onur Topaloglu; Swaroop Ghosh (ACM Great Lakes Symposium on VLSI, 2022)

Quantum Machine Learning for Material Synthesis and Hardware Security (Invited Paper). - Collin Beaudoin; Satwik Kundu; Rasit Onur Topaloglu; Swaroop Ghosh (ICCAD, 2022)

Optimization of Quantum Read-Only Memory Circuits. - Koustubh Phalak; Mahabubul Alam; Abdullah Ash-Saki; Rasit Onur Topaloglu; Swaroop Ghosh (ICCD, 2022)

Shuttle-Exploiting Attacks and Their Defenses in Trapped-Ion Quantum Computers. - Abdullah Ash-Saki; Rasit Onur Topaloglu; Swaroop Ghosh (IEEE Access, 2022)

Quantum Machine Learning for Material Synthesis and Hardware Security. - Collin Beaudoin; Satwik Kundu; Rasit Onur Topaloglu; Swaroop Ghosh (CoRR, 2022)

On the Complexity of Generalized Discrete Logarithm Problem. - Cem M. Unsal; Rasit Onur Topaloglu (CoRR, 2022)

ObfusX: Routing obfuscation with explanatory analysis of a machine learning attack. - Wei Zeng 015; Azadeh Davoodi; Rasit Onur Topaloglu (Integr., 2023)

SCANN: Side Channel Analysis of Spiking Neural Networks. - Karthikeyan Nagarajan; Rupshali Roy; Rasit Onur Topaloglu; Sachhidh Kannan; Swaroop Ghosh (Cryptogr., 2023)

Florets for Chiplets: Data Flow-aware High-Performance and Energy-efficient Network-on-Interposer for CNN Inference Tasks. - Harsh Sharma; Lukas Pfromm; Rasit Onur Topaloglu; Janardhan Rao Doppa; Ümit Y. Ogras; Ananth Kalyanaraman; Partha Pratim Pande (ACM Trans. Embed. Comput. Syst., 2023)

ReBERT: LLM for Gate-Level to Word-Level Reverse Engineering. - Lizi Zhang; Azadeh Davoodi; Rasit Onur Topaloglu (DATE, 2025)