Investigating the Use of BICS to detect resistive-open defects in SRAMs. - Raul Chipana; Letícia Maria Veiras Bolzani; Fabian Vargas 001; Jorge Semião; Juan J. Rodríguez-Andina; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTS, 2010)

BICS-based March test for resistive-open defect detection in SRAMs. - Raul Chipana; Letícia Maria Veiras Bolzani; Fabian Vargas 001 (LATW, 2010)

Designing and analyzing a SpaceWire router IP for soft errors detection. - Jimmy Tarrillo; Raul Chipana; Eduardo Chielle; Fernanda Lima Kastensmidt (LATW, 2011)

Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction. - Costas Argyrides; Raul Chipana; Fabian Vargas 001; Dhiraj K. Pradhan (IEEE Trans. Reliab., 2011)

Soft-Error Probability Due to SET in Clock Tree Networks. - Raul Chipana; Eduardo Chielle; Fernanda Lima Kastensmidt; Jorge L. Tonfat; Ricardo Reis 001 (ISVLSI, 2012)

SET susceptibility estimation of clock tree networks from layout extraction. - Raul Chipana; Fernanda Lima Kastensmidt; Jorge L. Tonfat; Ricardo Reis 001 (LATW, 2012)

SET Susceptibility Analysis of Clock Tree and Clock Mesh Topologies. - Raul Chipana; Fernanda Gusmão de Lima Kastensmidt (ISVLSI, 2014)