Advanced and Intelligent Control Techniques Applied to the Drive Control and Path Tracking Systems on a Robotic Wheelchair. - Felipe Espinosa; Elena López Guillén; Raúl Mateos; Manuel Mazo 001; Ricardo García (Auton. Robots, 2001)

Mobile Robot with Wide Capture Active Laser Sensor and Environment Definition. - José Luis Lázaro; Alfredo Gardel Vicente; Manuel Mazo 001; C. Mataix; Juan C. García 001; Raúl Mateos (J. Intell. Robotic Syst., 2001)

Different proposals to the multiplication of 3×3 vision mask in VHDL for FPGA's. - Ignacio Bravo Muñoz; Álvaro Hernández; Alfredo Gardel Vicente; Raúl Mateos; José Luis Lázaro; V. Diaz (ETFA (2), 2003)

Lossless implementation in VHDL of an image wavelet transform. - Raúl Mateos; Alfredo Gardel Vicente; Álvaro Hernández; Ignacio Bravo Muñoz; C. Garcia (ETFA (2), 2003)

Hardware/software co-simulation environment for CSoC with soft processors. - Raúl Mateos; José Luis Lázaro; Felipe Espinosa (FPT, 2004)

A DSP- and FPGA-Based Industrial Control With High-Speed Communication Interfaces for Grid Converters Applied to Distributed Power Generation Systems. - Emilio José Bueno; Álvaro Hernández; Francisco J. Rodríguez 001; Carlos Giron; Raúl Mateos; Santiago Cóbreces (IEEE Trans. Ind. Electron., 2009)

A Strict-Time Distributed Architecture for Digital Beamforming of Ultrasound Signals. - Jorge Camacho; Oscar Martinez; Montserrat Parrilla; Raúl Mateos; Carlos Fritsch (IEEE Trans. Instrum. Meas., 2010)

Comparative of HLS and HDL implementations of a grid synchronization algorithm. - Fco. Manuel Sánchez; Raúl Mateos; Emilio José Bueno; Javier Mingo; Ines Sanz (IECON, 2013)

FPGA-based implementation of a filter bank-based transmultiplexer for multicarrier communications. - Pablo Poudereux; Raúl Mateos; Álvaro Hernández; Fernando Cruz-Roldán; David Oses (ETFA, 2014)

Study of suitable filter architectures for FBMC techniques applied to PLC communications. - Pablo Poudereux; Raúl Mateos; Álvaro Hernández; Francisco Nombela; Fernando Cruz-Roldán (ETFA, 2015)

Efficient Implementation of a Symbol Timing Estimator for Broadband PLC. - Francisco Nombela; Enrique García; Raúl Mateos; Álvaro Hernández (Sensors, 2015)

Design of a filter bank multi-carrier system for broadband power line communications. - Pablo Poudereux; Álvaro Hernández; Raúl Mateos; Freddy A. Pinto-Benel; Fernando Cruz-Roldán (Signal Process., 2016)

Finite Precision Analysis of FPGA-based Architecture for FBMC Transmultiplexers in Broadband PLC. - Rubén Nieto; Raúl Mateos; Álvaro Hernández (DCIS, 2018)

FPGA-Based Architecture for Medium Access Techniques in Broadband PLC. - Pablo Poudereux; Álvaro Hernández; Fernando Cruz-Roldán; Raúl Mateos (IEEE Access, 2018)

Dual-Core Architecture for PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer. - Rubén Nieto; Raúl Mateos; Álvaro Hernández; Edel Díaz (ETFA, 2019)

Virtual Platform of FPGA based MPSoC for Power Electronics Applications: OS simulation. - Edel Díaz; Raúl Mateos; Emilio José Bueno (IECON, 2019)

Virtual Platform of FPGA based SoC for Power Electronics Applications. - Edel Díaz; Raúl Mateos; Emilio José Bueno (ISIE, 2019)

Real-time architecture for channel estimation and equalization in broadband PLC. - Francisco Nombela; Enrique García; Raúl Mateos; Álvaro Hernández (Microprocess. Microsystems, 2019)

Distortion-Free Instantaneous Multifrequency Saturator for THD Current Reduction. - Javier Moriano; Mario Rizo; Emilio Bueno; J. Rafael Sendra; Raúl Mateos (IEEE Trans. Ind. Electron., 2019)

Evaluation of Software Inter-Processor Synchronization Methods for the Zynq-UltraScale+ Architecture. - Rubén Nieto; Edel Díaz; Raúl Mateos; Álvaro Hernández (DCIS, 2020)

Performance Improvement of PLC Channel Estimator and ASCET Equalizer in a FBMC Transmultiplexer Based on a Multi-Core Solution. - Rubén Nieto; Raúl Mateos; Álvaro Hernández (IEEE Access, 2020)

HW/SW Architecture for a Broadband Power-Line Communication System With LS Channel Estimator and ASCET Equalizer. - Rubén Nieto; Raúl Mateos; Álvaro Hernández (IEEE Trans. Ind. Informatics, 2020)