Design and Implementation of Systolic Architectures for Vector Quantization. - Ravi K. Kolagotla (1992)

Optimal unified IIR architectures for time-recursive discrete sinusoidal transforms. - Kuo J. Ray Liu; Ching-Te Chiu; Ravi K. Kolagotla; Joseph F. JáJá (ICASSP (3), 1993)

VLSI implementation of a tree searched vector quantizer. - Ravi K. Kolagotla; Shu-sun Yu; Joseph F. JáJá (IEEE Trans. Signal Process., 1993)

Systolic architectures for finite-state vector quantization. - Ravi K. Kolagotla; Shu-sun Yu; Joseph F. JáJá (J. VLSI Signal Process., 1993)

Optimal unified architectures for the real-time computation of time-recursive discrete sinusoidal transforms. - K. J. Ray Liu; Ching-Te Chiu; Ravi K. Kolagotla; Joseph F. JáJá (IEEE Trans. Circuits Syst. Video Technol., 1994)

Design and implementation of a 16 by 16 low-power two's complement multiplier. - Alexander Goldovsky; Bimal Patel; Michael Schulte 003; Ravi K. Kolagotla; Hosahalli Srinivas; Geoffrey Burns (ISCAS, 2000)

A 333-MHz dual-MAC DSP architecture for next-generation wireless applications. - Ravi K. Kolagotla; José Fridman; Marc M. Hoffman; William C. Anderson; Bradley C. Aldrich; David B. Witt; Michael S. Allen; Randy R. Dunton; Lawrence A. Booth Jr. (ICASSP, 2001)

High performance dual-MAC DSP architecture. - Ravi K. Kolagotla; José Fridman; Bradley C. Aldrich; Marc M. Hoffman; William C. Anderson; Michael S. Allen; David B. Witt; Randy R. Dunton; Lawrence A. Booth Jr. (IEEE Signal Process. Mag., 2002)

Addressing mode driven low power data caches for embedded processors. - Ramesh V. Peri; John Fernando; Ravi K. Kolagotla (WMPI, 2004)

Introduction to the Special Issue on the IEEE 2006 Custom Integrated Circuits Conference. - Ravi K. Kolagotla; Krzysztof Iniewski; Ranjit Gharpurey (IEEE J. Solid State Circuits, 2007)