A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays. - Ravi Tej Uppu; Ravi Kanth Uppu; Adit D. Singh; Abhijit Chatterjee (VLSI Design, 2013)

Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. - Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh; Ilia Polian (VLSID, 2014)