Improving the Throughput of Synchronization by Insertion of Delays. - Ravi Rajwar; Alain Kägi; James R. Goodman (HPCA, 2000)

An Architectural Evaluation of Java TPC-W. - Harold W. Cain; Ravi Rajwar; Morris Marden; Mikko H. Lipasti (HPCA, 2001)

Speculative lock elision: enabling highly concurrent multithreaded execution. - Ravi Rajwar; James R. Goodman (MICRO, 2001)

Transactional lock-free execution of lock-based programs. - Ravi Rajwar; James R. Goodman (ASPLOS, 2002)

Inferential queueing and speculative push for reducing critical communication latencies. - Ravi Rajwar; Alain Kägi; James R. Goodman (ICS, 2003)

Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. - Haitham Akkary; Ravi Rajwar; Srikanth T. Srinivasan (MICRO, 2003)

Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers. - Haitham Akkary; Ravi Rajwar; Srikanth T. Srinivasan (IEEE Micro, 2003)

Transactional Execution: Toward Reliable, High-Performance Multithreading. - Ravi Rajwar; James R. Goodman (IEEE Micro, 2003)

Continual flow pipelines. - Srikanth T. Srinivasan; Ravi Rajwar; Haitham Akkary; Amit Gandhi; Michael Upton (ASPLOS, 2004)

Inferential Queueing and Speculative Push. - Ravi Rajwar; Alain Kägi; James R. Goodman (Int. J. Parallel Program., 2004)

Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance. - Srikanth T. Srinivasan; Ravi Rajwar; Haitham Akkary; Amit Gandhi; Michael Upton (IEEE Micro, 2004)

An analysis of a resource efficient checkpoint architecture. - Haitham Akkary; Ravi Rajwar; Srikanth T. Srinivasan (ACM Trans. Archit. Code Optim., 2004)

The Impact of Performance Asymmetry in Emerging Multicore Architectures. - Saisanthosh Balakrishnan; Ravi Rajwar; Michael Upton; Konrad K. Lai (ISCA, 2005)

Virtualizing Transactional Memory. - Ravi Rajwar; Maurice Herlihy; Konrad K. Lai (ISCA, 2005)

Atomicity as a First-Class System Provision. - J. Eliot B. Moss; Ravi Rajwar (J. Univers. Comput. Sci., 2005)

The atomic manifesto: a story in four quarks. - Cliff B. Jones; David B. Lomet; Alexander B. Romanovsky; Gerhard Weikum; Alan D. Fekete; Marie-Claude Gaudel; Henry F. Korth; Rogério de Lemos; J. Eliot B. Moss; Ravi Rajwar; Krithi Ramamritham; Brian Randell; et al. (SIGMOD Rec., 2005)

Scalable Load and Store Processing in Latency-Tolerant Processors. - Amit Gandhi; Haitham Akkary; Ravi Rajwar; Srikanth T. Srinivasan; Konrad Lai (IEEE Micro, 2006)

Transactional Memory - James R. Larus; Ravi Rajwar (Morgan & Claypool Publishers, 2006)

Implications of False Conflict Rate Trends for Robust Software Transactional Memory. - Craig B. Zilles; Ravi Rajwar (IISWC, 2007)

Hardware atomicity for reliable software speculation. - Naveen Neelakantam; Ravi Rajwar; Suresh Srinivas; Uma Srinivasan 003; Craig B. Zilles (ISCA, 2007)

Transactional memory and the birthday paradox. - Craig B. Zilles; Ravi Rajwar (SPAA, 2007)

Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation. - Naveen Neelakantam; Ravi Rajwar; Suresh Srinivas; Uma Srinivasan 003; Craig B. Zilles (IEEE Micro, 2008)

Transactional Memory, 2nd Edition - Tim Harris 001; James R. Larus; Ravi Rajwar (Transactional Memory (2.Ed.), 2010)

In search of parallel dimensions. - Ravi Rajwar (SPAA, 2012)

Performance evaluation of Intel® transactional synchronization extensions for high-performance computing. - Richard M. Yoo; Christopher J. Hughes; Konrad Lai; Ravi Rajwar (SC, 2013)

Improving in-memory database index performance with Intel® Transactional Synchronization Extensions. - Tomas Karnagel; Roman Dementiev; Ravi Rajwar; Konrad Lai; Thomas Legler; Benjamin Schlegel; Wolfgang Lehner (HPCA, 2014)

Haswell: The Fourth-Generation Intel Core Processor. - Per Hammarlund; Alberto J. Martinez; Atiq A. Bajwa; David L. Hill; Erik G. Hallnor; Hong Jiang; Martin G. Dixon; Michael Derr; Mikal Hunsaker; Rajesh Kumar; Randy B. Osborne; Ravi Rajwar; et al. (IEEE Micro, 2014)

Specialized Evolution of the General Purpose CPU. - Ravi Rajwar; Martin G. Dixon; Ronak Singhal (CIDR, 2015)

Haswell: A Family of IA 22 nm Processors. - Nasser A. Kurd; Muntaquim Chowdhury; Edward Burton; Thomas P. Thomas; Christopher Mozak; Brent Boswell; Praveen Mosalikanti; Mark Neidengard; Anant Deval; Ashish Khanna; Nasirul Chowdhury; Ravi Rajwar; et al. (IEEE J. Solid State Circuits, 2015)

Towards an Adaptable Systems Architecture for Memory Tiering at Warehouse-Scale. - Padmapriya Duraisamy; Wei Xu; Scott Hare; Ravi Rajwar; David E. Culler; Zhiyi Xu; Jianing Fan; Christopher Kennelly; Bill McCloskey; Danijela Mijailovic; Brian Morris; Chiranjit Mukherjee; et al. (ASPLOS (3), 2023)