A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS. - Behrooz Abiri; Ravi Shivnaraine; Ali Sheikholeslami; Hirotaka Tamura; Masaya Kibune (ISSCC, 2011)

An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection. - Mohammad Sadegh Jalali; Ravi Shivnaraine; Ali Sheikholeslami; Masaya Kibune; Hirotaka Tamura (CICC, 2013)

An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset". - Ravi Shivnaraine; Mohammad Sadegh Jalali; Ali Sheikholeslami; Masaya Kibune; Hirotaka Tamura (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS. - Ravi Shivnaraine; Marcus van Ierssel; Kamran Farzan; Dominic DiClemente; George Ng; Nanyan Wang; Javid Musayev; Gairik Dutta; Masumi Shibata; Arash Moradi; Haleh Vahedi; Manavi Farzad; et al. (ISSCC, 2021)