Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell. - Jared L. Zerbe; Carl W. Werner; Vladimir Stojanovic; Fred Chen; Jason Wei; Grace Tsang; Dennis Kim; William F. Stonecypher; Andrew Ho; Timothy P. Thrush; Ravi T. Kollipara; Mark A. Horowitz; et al. (IEEE J. Solid State Circuits, 2003)

Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery. - Vladimir Stojanovic; Andrew Ho; Bruno W. Garlepp; Fred Chen; Jason Wei; Grace Tsang; Elad Alon; Ravi T. Kollipara; Carl W. Werner; Jared L. Zerbe; Mark A. Horowitz (IEEE J. Solid State Circuits, 2005)

A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter. - Amir Amirkhany; Aliazam Abbasfar; Jafar Savoj; Metha Jeeradit; Bruno W. Garlepp; Ravi T. Kollipara; Vladimir Stojanovic; Mark Horowitz (IEEE J. Solid State Circuits, 2008)

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques. - Jared Zerbe; Barry Daly; Lei Luo 006; Bill Stonecypher; Wayne D. Dettloff; John C. Eble; Teva Stone; Jihong Ren; Brian S. Leibowitz; Michael Bucher; Patrick Satarzadeh; Qi Lin; et al. (IEEE J. Solid State Circuits, 2011)

A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems. - Kambiz Kaviani; Michael Bucher; Bruce Su; Barry Daly; Bill Stonecypher; Wayne D. Dettloff; Teva Stone; Kashinath Prabhu; Pravin Kumar Venkatesan; Fred Heaton; Ravi T. Kollipara; Yi Lu; et al. (ISSCC, 2013)

A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems. - Michael Bucher; Ravi T. Kollipara; Bruce Su; Liji Gopalakrishnan; Kashinath Prabhu; Pravin Kumar Venkatesan; Kambiz Kaviani; Barry Daly; William F. Stonecypher; Wayne D. Dettloff; Teva Stone; Fred Heaton; et al. (IEEE J. Solid State Circuits, 2014)