5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor. - Aaron Grenat; Sanjay Pant; Ravinder Rachala; Samuel Naffziger (ISSCC, 2014)

Steamroller Module and Adaptive Clocking System in 28 nm CMOS. - Kathryn Wilcox; Robert Cole; Harry R. Fair III; Kevin Gillespie; Aaron Grenat; Carson Henrion; Ravi Jotwani; Stephen Kosonocky; Benjamin Munger; Samuel Naffziger; Robert S. Orefice; Sanjay Pant; et al. (IEEE J. Solid State Circuits, 2015)

Modeling and implementation of a fully-digital integrated per-core voltage regulation system in a 28nm high performance 64-bit processor. - Ravinder Rachala; Miguel Rodriguez; Stephen Kosonocky; Milos Trajkovic (ISLPED, 2016)

4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. - Aaron Grenat; Sriram Sundaram; Stephen Kosonocky; Ravinder Rachala; Sriram Sambamurthy; Steven Liepe; Miguel Rodriguez; Tom Burd; Adam Clark; Michael Austin; Samuel Naffziger (ISSCC, 2016)

Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management. - Sriram Sundaram; Aaron Grenat; Samuel Naffziger; Tom Burd; Stephen Kosonocky; Steven Liepe; Ravinder Rachala; Miguel Rodriguez; Michael Austin; Sriram Sambamurthy (IEEE J. Solid State Circuits, 2017)