Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment. - Ravindranath Naiknaware (ICCD, 1993)

Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation. - Ravindranath Naiknaware; G. N. Nandakumar; Srinivasa Rao Kasa (ITC, 1993)

Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. - Ravindranath Naiknaware; G. N. Nandakumar; Rajeev Arora; John Larkin (VLSI Design, 1993)

Schematic driven module generation for analog circuits with performance optimization and matching considerations. - Ravindranath Naiknaware; Terri S. Fiez (CICC, 1998)

CMOS analog circuit stack generation with matching constraints. - Ravindranath Naiknaware; Terri S. Fiez (ICCAD, 1998)

Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer. - Ravindranath Naiknaware; Terri S. Fiez (ISCAS (2), 1999)

Switched-capacitor integrator design optimizing for power and process variations. - Ravindranath Naiknaware; Terri S. Fiez (ISCAS (2), 1999)

Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations. - Ravindranath Naiknaware; Terri S. Fiez (IEEE J. Solid State Circuits, 1999)

142 dB ΔΣ ADC with a 100 nV LSB in a 3 V CMOS process. - Ravindranath Naiknaware; Terri S. Fiez (CICC, 2000)

Process-insensitive low-power design of switched-capacitor integrators. - Ravindranath Naiknaware; Terri S. Fiez (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)