CMOS Gate Delay Models for General RLC Loading. - Ravishankar Arunachalam; Florentin Dartu; Lawrence T. Pileggi (ICCD, 1997)

Determination of worst-case aggressor alignment for delay calculation. - Paul D. Gross; Ravishankar Arunachalam; Karthik Rajagopal; Lawrence T. Pileggi (ICCAD, 1998)

TACO: timing analysis with coupling. - Ravishankar Arunachalam; Karthik Rajagopal; Lawrence T. Pileggi (DAC, 2000)

False Coupling Interactions in Static Timing Analysis. - Ravishankar Arunachalam; Ronald D. Blanton; Lawrence T. Pileggi (DAC, 2001)

Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation. - Ravishankar Arunachalam; Ronald DeShawn Blanton; Lawrence T. Pileggi (VLSI Design, 2002)

Predicting short circuit power from timing models. - Emrah Acar; Ravishankar Arunachalam; Sani R. Nassif (ASP-DAC, 2003)

Optimal shielding/spacing metrics for low power design. - Ravishankar Arunachalam; Emrah Acar; Sani R. Nassif (ISVLSI, 2003)

Static Transition Probability Analysis Under Uncertainty. - Siddharth Garg; Siddharth Tata; Ravishankar Arunachalam (ICCD, 2004)

Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits. - Aniket; Ravishankar Arunachalam (VLSI Design, 2005)