A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS. - Raviteja Kammari; Vijaya Sankara Rao Pasupureddi (VDAT, 2019)

Charge controlled delay element enabled widely linear power efficient MPCG-MDLL in 1.2V, 65nm CMOS. - Raviteja Kammari; Vijaya Sankara Rao Pasupureddi (Int. J. Circuit Theory Appl., 2020)

Digitally Intensive Sub-sampling Mixer-First Direct Down-Conversion Receiver Architecture. - Rakesh Rena; Raviteja Kammari; Vijaya Sankara Rao Pasupureddi (MWSCAS, 2022)

A 1-6 GHz, Sub-mW Self-Aligned Quadrature Phase Clock Generator in 1.2 V, 65 nm CMOS. - Raviteja Kammari; Sarvesh Rajesh Tuckely; Vijay Shankar Pasupureddi (APCCAS, 2023)

0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, +10-dBm IB-IIP3 in 65-nm CMOS. - Rakesh Varma Rena; Raviteja Kammari; Vijay Shankar Pasupureddi (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An adaptive link training based hybrid circuit topology for full-duplex on-chip interconnects. - Prema Kumar Govindaswamy; Raviteja Kammari; Vijaya Sankara Rao Pasupureddi (Int. J. Circuit Theory Appl., 2023)

A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End. - Rakesh Varma Rena; Raviteja Kammari; Vijay Shankar Pasupureddi (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Breaking the Trade-off Between Input Impedance and Mixer Paths in Sub-Harmonic N-Path Mixer-First RF Front-end. - Raviteja Kammari; Vijay Shankar Pasupureddi (ISCAS, 2025)

A ±0.6 dB, 256-μW Digital-Intensive RSSI with 80-dB Dynamic-Range in 65-nm CMOS. - Sivaiah Naali; Ravi Prakash Bisen; Raviteja Kammari; Vijay Shankar Pasupureddi (ISCAS, 2025)