Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs. - Rawat Siripokarpirom (FPL, 2004)

Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-Based Rapid Prototyping Boards. - Rawat Siripokarpirom; Friedrich Mayer-Lindenberg (IEEE International Workshop on Rapid System Prototyping, 2004)

A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and Test. - Rawat Siripokarpirom (FPL, 2005)

Platform Development for Run-Time Reconfigurable Co-Emulation. - Rawat Siripokarpirom (IEEE International Workshop on Rapid System Prototyping, 2006)