A 6-ns cycle 256-kb cache memory and memory management unit. - Raymond A. Heald; John Holst (IEEE J. Solid State Circuits, 1993)

A CMOS Circuit for Real-Time Chip Temperature Measurement. - Steven R. Boyle; Raymond A. Heald (COMPCON, 1994)

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. - Raymond A. Heald; Ken Shin; Vinita Reddy; I-Feng Kao; Masood Khan; William L. Lynch; Gary Lauterbach; Joe Petolino (IEEE J. Solid State Circuits, 1998)

A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors. - Fabian Klass; Chaim Amir; Ashutosh Das; Kathirgamar Aingaran; Cindy Truong; Richard Wang; Anup Mehta; Raymond A. Heald; Gin Yee (IEEE J. Solid State Circuits, 1999)

A third-generation SPARC V9 64-b microprocessor. - Raymond A. Heald; Kathirgamar Aingaran; Chaim Amir; Michael Ang; Michael Boland; Pankaj Dixit; Gary Gouldsberry; Dale Greenley; Joel Grinberg; Jason M. Hart; Tim Horel; Wen-Jay Hsu; et al. (IEEE J. Solid State Circuits, 2000)

Variability in sub-100nm SRAM designs. - Raymond A. Heald; Ping Wang (ICCAD, 2004)

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor. - Hugh McIntyre; Dennis Wendell; K. James Lin; P. Kaushik; Suresh Seshadri; Alfred Wang; V. Sundararaman; Ping Wang; Song Kim; Wen-Jay Hsu; Hee-Choul Park; Gideon Levinsky; et al. (IEEE J. Solid State Circuits, 2005)