Quaternary logic circuits in 2- mu m CMOS technology. - Naresh R. Shanbhag; Dipankar Nagchoudhuri; Raymond E. Siferd; Gangaikondan S. Visweswaran (IEEE J. Solid State Circuits, 1990)

A single-chip pipelined 2-D FIR filter using residue arithmetic. - Naresh R. Shanbhag; Raymond E. Siferd (IEEE J. Solid State Circuits, 1991)

Cmos PWM Control Circuit with Programmable Dead Time. - Raymond E. Siferd; Robert Cravens II; Marian K. Kazimierczuk (J. Circuits Syst. Comput., 1995)

An Adaptive noise canceler Implemented with CMOS Analog Technology. - Gabriel Gomez; Raymond E. Siferd (J. Circuits Syst. Comput., 1996)

High Performance CMOS Analog Arithmetic Circuits. - Jing Xu; Raymond E. Siferd; Robert L. Ewing (J. VLSI Signal Process., 1999)

VLSI Implementation of a Low-Power Antilogarithmic Converter. - Khalid H. Abed; Raymond E. Siferd (IEEE Trans. Computers, 2003)

CMOS VLSI Implementation of a Low-Power Logarithmic Converter. - Khalid H. Abed; Raymond E. Siferd (IEEE Trans. Computers, 2003)

Parallel time interleaved delta sigma band pass analog to digital converter for SOC applications. - Saiyu Ren; Ray Siferd; Robert Blumgold (SoCC, 2004)

Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS. - Saiyu Ren; Ray Siferd (SoCC, 2009)

CMOS 1.6 GHz Bandwidth 12 Bit Time Interleaved Pipelined ADC. - Saiyu Ren; Ray Siferd (ITNG, 2011)

Logistic Function Based Memristor Model With Circuit Application. - Isaac Abraham; Saiyu Ren; Raymond E. Siferd (IEEE Access, 2019)

A 170 MHz to 330 MHz Wideband 90 nm CMOS RC-CR Phase Shifter with Integrated On-Line Amplitude Locked Loop Calibration for Hartley Image Rejection Transceiver. - Xiaomeng Zhang; Shuo Li; Ray Siferd; Saiyu Ren (Circuits Syst. Signal Process., 2021)