An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation. - Seung-Yong Lim; Raymond Mabilangan; Dong-Jin Chang; Young-Jae Cho; Michael Choi; Seung-Tak Ryu (A-SSCC, 2021)

A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA. - Bo Gao; Lizhen Zhang; Raymond Mabilangan; Chang-Un Park; Kent Edrian Lozada; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (A-SSCC, 2024)

DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation. - Lizhen Zhang; Bo Gao; Kun-Woo Park; Kent Edrian Lozada; Raymond Mabilangan; Hyeongjin Kim; Jianhui Wu 001; Seung-Tak Ryu (IEEE Open J. Circuits Syst., 2024)