A Fine-Grain Parallel Architecture Based on Barrier Synchronization. - Henry G. Dietz; Raymond Hoare; Timothy Mattox (ICPP, Vol. 1, 1996)

Bitwise aggregate networks. - Raymond Hoare; Henry G. Dietz; Timothy Mattox; Soohong P. Kim (SPDP, 1996)

VLIW Across Multiple Superscalar Processors on a Single Chip. - Soohong P. Kim; Raymond Hoare; Henry G. Dietz (IEEE PACT, 1997)

A Case for Aggregate Networks. - Raymond Hoare; Henry G. Dietz (IPPS/SPDP, 1998)

ClusterNet: An Object-Oriented Cluster Network. - Raymond Hoare (IPDPS Workshops, 2000)

Cyclical Cascade Chains: A Dynamic Barrier Synchronization Mechanism for Multiprocessor Systems. - Troy A. Johnson; Raymond R. Hoare (IPDPS, 2001)

An SoC Solution for Massive Parallel Processing. - David Reed; Raymond Hoare (IPDPS, 2002)

A Width Expansion of MMX/SIMD Processing Architecture on an FPGA. - Raymond R. Hoare; D. Swope; S. Bailey (IASTED PDCS, 2002)

Cross-institutional assessment: Development and implementation of the On-line Student Survey System. - Raymond Hoare; Mary Besterfield-Sacre; Dan Ertman; Jessica Gerchak; Troy A. Johnson; Robert Shields; Larry J. Shuman (Comput. Appl. Eng. Educ., 2002)

Combining Mentor Graphics? HDL Designer FPGA Flow with a Reconfigurable System on a Programmable Chip, Educational Opportunity or Insanity? - Raymond Hoare; Shen Chih Tung (MSE, 2003)

Short Courses in System-on-a-Chip (SoC) Design. - Ivan S. Kourtev; Raymond R. Hoare; Steven P. Levitan; Tom Cain; Bruce R. Childers; Donald M. Chiarulli; David L. Landis (MSE, 2003)

A 64-way VLIW/SIMD FPGA architecture and design flow. - Alex K. Jones; Raymond Hoare; Ivan S. Kourtev; Joshua Fazekas; Dara Kusic; John Foster 001; Sedric Boddie; Ahmed Muaydh (ICECS, 2004)

LURU: global-scope FPGA technology mapping with content-addressable memories. - Joshua M. Lucas; Raymond R. Hoare; Ivan S. Kourtev; Alex K. Jones (ICECS, 2004)

An 88-Way Multiprocessor within an FPGA with Customizable Instructions. - Raymond Hoare; Shen Chih Tung; Katrina Werger (IPDPS, 2004)

Optimizing Technology Mapping for FPGAs Using CAMs. - Joshua M. Lucas; Raymond Hoare; Alex K. Jones (FCCM, 2005)

An FPGA-based VLIW processor with custom hardware execution. - Alex K. Jones; Raymond Hoare; Dara Kusic; Joshua Fazekas; John Foster 001 (FPGA, 2005)

Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks. - Zhu Ding; Raymond R. Hoare; Alex K. Jones; Dan Li; Shou-Kuo Shao; Shen-Chien Tung; Jiang Zheng 002; Rami G. Melhem (IPDPS, 2005)

Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. - Dara Kusic; Raymond Hoare; Alex K. Jones; Joshua Fazekas; John Foster 001 (IPDPS, 2005)

On the Feasibility of Optical Circuit Switching for High Performance Computing Systems. - Kevin J. Barker; Alan F. Benner; Raymond R. Hoare; Adolfy Hoisie; Alex K. Jones; Darren J. Kerbyson; Dan Li; Rami G. Melhem; Ramakrishnan Rajamony; Eugen Schenfeld; Shuyi Shao; Craig B. Stunkel; et al. (SC, 2005)

A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks. - Raymond R. Hoare; Zhu Ding; Shen Chih Tung; Rami G. Melhem; Alex K. Jones (J. Parallel Distributed Comput., 2005)

An automated, reconfigurable, low-power RFID tag. - Alex K. Jones; Raymond R. Hoare; Swapna R. Dontharaju; Shen Chih Tung; Ralph Sprang; Joshua Fazekas; James T. Cain; Marlin H. Mickle (DAC, 2006)

Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). - Raymond R. Hoare; Ivan S. Kourtev; Alex K. Jones (FCCM, 2006)

A Field Programmable RFID Tag and Associated Design Flow. - Alex K. Jones; Raymond R. Hoare; Swapna R. Dontharaju; Shen Chih Tung; Ralph Sprang; Joshua Fazekas; James T. Cain; Marlin H. Mickle (FCCM, 2006)

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. - Gayatri Mehta; Raymond R. Hoare; Justin Stander; Alex K. Jones (FCCM, 2006)

Design space exploration for low-power reconfigurable fabrics. - Gayatri Mehta; Raymond R. Hoare; Justin Stander; Alex K. Jones (IPDPS, 2006)

Speech silicon AM: an FPGA-based acoustic modeling pipeline for hidden Markov model based speech recognition. - Jeffrey William Schuster; Kshitij Gupta; Raymond R. Hoare (IPDPS, 2006)

A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory. - Ying Yu; Raymond R. Hoare; Alex K. Jones; Ralph Sprang (ISCAS, 2006)

Interconnect routing and scheduling - Level-wise scheduling algorithm for fat tree interconnection networks. - Zhu Ding; Raymond R. Hoare; Alex K. Jones; Rami G. Melhem (SC, 2006)

Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches. - Raymond R. Hoare; Zhu Ding; Alex K. Jones (SC, 2006)

Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions. - Raymond R. Hoare; Alex K. Jones; Dara Kusic; Joshua Fazekas; John Foster 001; Shen Chih Tung; Michael L. McCloud (EURASIP J. Adv. Signal Process., 2006)

Speech Silicon: An FPGA Architecture for Real-Time Hidden Markov-Model-Based Speech Recognition. - Jeffrey William Schuster; Kshitij Gupta; Raymond Hoare; Alex K. Jones (EURASIP J. Embed. Syst., 2006)

Passive active radio frequency identification tags. - Alex K. Jones; Swapna R. Dontharaju; Shen Chih Tung; Peter J. Hawrylak; Leonid Mats; Raymond R. Hoare; James T. Cain; Marlin H. Mickle (Int. J. Radio Freq. Identif. Technol. Appl., 2006)

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. - Gayatri Mehta; Justin Stander; Joshua M. Lucas; Raymond R. Hoare; Brady Hunsaker; Alex K. Jones (J. Low Power Electron., 2006)

Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). - Joshua M. Lucas; Raymond Hoare; Ivan S. Kourtev; Alex K. Jones (Microprocess. Microsystems, 2006)

A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power. - Alex K. Jones; Raymond R. Hoare; Dara Kusic; Justin Stander; Gayatri Mehta; Joshua Fazekas (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Reducing power while increasing performance with supercisc. - Alex K. Jones; Raymond Hoare; Dara Kusic; Gayatri Mehta; Joshua Fazekas; John Foster 001 (ACM Trans. Embed. Comput. Syst., 2006)

Linking Compilation and Visualization for Massively Parallel Programs. - Alex K. Jones; Raymond R. Hoare; Joseph St. Onge; Joshua M. Lucas; Shuyi Shao; Rami G. Melhem (IPDPS, 2007)

An automated, FPGA-based reconfigurable, low-power RFID tag. - Alex K. Jones; Raymond Hoare; Swapna R. Dontharaju; Shen Chih Tung; Ralph Sprang; Joshua Fazekas; James T. Cain; Marlin H. Mickle (Microprocess. Microsystems, 2007)

A CAM-based intrusion detection system for single-packet attack detection. - Ying Yu; Raymond R. Hoare; Alex K. Jones (IPDPS, 2008)

A two-stage hardware scheduler combining greedy and optimal scheduling. - Raymond R. Hoare; Zhu Ding; Alex K. Jones (J. Parallel Distributed Comput., 2008)

Radio frequency identification prototyping. - Alex K. Jones; Swapna R. Dontharaju; Shen Chih Tung; Leonid Mats; Peter J. Hawrylak; Raymond R. Hoare; James T. Cain; Marlin H. Mickle (ACM Trans. Design Autom. Electr. Syst., 2008)

Accelerating SAR processing on COTS FPGA hardware using C-to-gates design tools. - Raymond R. Hoare; Denis Smetana (HPEC, 2014)