A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology. - Hossein Ghasemian; Razieh Ghasemi; Ebrahim Abiri; Mohammad Reza Salehi (Microelectron. J., 2019)

A 10-bit 1GSample/s hybrid digital-to-analog converter with a modified thermometer decoder in 65-nm CMOS technology. - Razieh Ghasemi; Mohammad Azim Karami (Int. J. Circuit Theory Appl., 2022)

Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bits. - Ayoub Sadeghi; Razieh Ghasemi; Hossein Ghasemian; Nabiollah Shiri (Frontiers Inf. Technol. Electron. Eng., 2023)

High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures. - Ayoub Sadeghi; Razieh Ghasemi; Hossein Ghasemian; Nabiollah Shiri (IEEE Embed. Syst. Lett., 2023)

A low phase noise quadrature VCO using super-harmonic coupling technique in 65-nm CMOS technology. - Razieh Ghasemi; Mohammad Azim Karami (Int. J. Circuit Theory Appl., 2024)

A Low-Power 10-Bit 2GS/s Hybrid Time-Interleaved Digital-to-Analog Converter with a New Neutrolized-Glitch Unit Current Cell in 65 nm CMOS Technology. - Razieh Ghasemi; Mohammad Azim Karami (Circuits Syst. Signal Process., 2024)