Real-time FPGA implementation of a secure chaos-based digital crypto-watermarking system in the DWT domain using co-design approach. - Redouane Kaibou; Mohamed Salah Azzaz; Mustapha Benssalah; Djamel Teguig; Hocine Hamil; Amira Merah; Meriam Tinhinane Akrour (J. Real Time Image Process., 2021)

Design of a secured telehealth system based on multiple biosignals diagnosis and classification for IoT application. - Hocine Hamil; Zahia Zidelmal; Mohamed Salah Azzaz; Samir Sakhi; Redouane Kaibou; Salem Djilali; Djaffar Ould Abdeslam (Expert Syst. J. Knowl. Eng., 2022)

A new hardware architecture of lightweight and efficient real-time video chaos-based encryption algorithm. - Mahieddine Anouar Hadjadj; Said Sadoudi; Mohamed Salah Azzaz; Hichem Bendecheche; Redouane Kaibou (J. Real Time Image Process., 2022)

Design of a New Hardware IP-HLS for Real-Time Image Chaos-Based Encryption. - Mohamed Salah Azzaz; Redouane Kaibou; Hamdane Kamelia; Abdenour Kifouche; Djamel Teguig (SECRYPT, 2023)

Co-design based FPGA implementation of an efficient new speech hyperchaotic cryptosystem in the transform domain. - Mohamed Salah Azzaz; Redouane Kaibou; Bachir Madani (Integr., 2024)

Efficient FPGA implementation of chaos-based real-time video watermarking system in spatial and DWT domain using QIM technique. - Noureddine Aissaoui; Mohamed Salah Azzaz; Redouane Kaibou; Camel Tanougast (J. Real Time Image Process., 2025)

Fast and efficient hardware architecture of Chebyshev polynomials algorithm for resisting to side channel attacks. - Bachir Madani; Mohamed S. Azzaz; Said Sadoudi; Redouane Kaibou (J. Supercomput., 2025)

Optimized Modular Adder Architecture for Cryptographic Applications on FPGAs. - Bachir Madani; Mohamed Salah Azzaz; Said Sadoudi; Redouane Kaibou; Bruno da Silva 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)