Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects. - Dongkook Park; Reetuparna Das; Chrysostomos Nicopoulos; Jongman Kim; Narayanan Vijaykrishnan; Ravishankar R. Iyer 001; Chita R. Das (Hot Interconnects, 2007)

A novel dimensionally-decomposed router for on-chip communication in 3D architectures. - Jongman Kim; Chrysostomos Nicopoulos; Dongkook Park; Reetuparna Das; Yuan Xie 001; Narayanan Vijaykrishnan; Mazin S. Yousif; Chita R. Das (ISCA, 2007)

Performance and power optimization through data compression in Network-on-Chip architectures. - Reetuparna Das; Asit K. Mishra; Chrysostomos Nicopoulos; Dongkook Park; Vijaykrishnan Narayanan; Ravishankar R. Iyer 001; Mazin S. Yousif; Chita R. Das (HPCA, 2008)

MIRA: A Multi-layered On-Chip Interconnect Router Architecture. - Dongkook Park; Soumya Eachempati; Reetuparna Das; Asit K. Mishra; Yuan Xie 001; Narayanan Vijaykrishnan; Chita R. Das (ISCA, 2008)

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. - Reetuparna Das; Soumya Eachempati; Asit K. Mishra; Narayanan Vijaykrishnan; Chita R. Das (HPCA, 2009)

Application-aware prioritization mechanisms for on-chip networks. - Reetuparna Das; Onur Mutlu; Thomas Moscibroda; Chita R. Das (MICRO, 2009)

A case for dynamic frequency tuning in on-chip networks. - Asit K. Mishra; Reetuparna Das; Soumya Eachempati; Ravishankar R. Iyer 001; Narayanan Vijaykrishnan; Chita R. Das (MICRO, 2009)

A case for integrated processor-cache partitioning in chip multiprocessors. - Shekhar Srikantaiah; Reetuparna Das; Asit K. Mishra; Chita R. Das; Mahmut T. Kandemir (SC, 2009)

Cost-driven 3D integration with interconnect layers. - Xiaoxia Wu; Guangyu Sun 003; Xiangyu Dong 001; Reetuparna Das; Yuan Xie 001; Chita R. Das; Jian Li 059 (DAC, 2010)

Aérgia: exploiting packet latency slack in on-chip networks. - Reetuparna Das; Onur Mutlu; Thomas Moscibroda; Chita R. Das (ISCA, 2010)

RAFT: A router architecture with frequency tuning for on-chip networks. - Asit K. Mishra; Aditya Yanamandra; Reetuparna Das; Soumya Eachempati; Ravi R. Iyer 001; Narayanan Vijaykrishnan; Chita R. Das (J. Parallel Distributed Comput., 2011)

Aérgia: A Network-on-Chip Exploiting Packet Latency Slack. - Reetuparna Das; Onur Mutlu; Thomas Moscibroda; Chita R. Das (IEEE Micro, 2011)

Application-to-core mapping policies to reduce memory interference in multi-core systems. - Reetuparna Das; Rachata Ausavarungnirun; Onur Mutlu; Akhilesh Kumar; Mani Azimi (PACT, 2012)

XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems. - Ronald G. Dreslinski; Thomas Manville; Korey Sewell; Reetuparna Das; Nathaniel Ross Pinckney; Sudhir Satpathy; David T. Blaauw; Dennis Sylvester; Trevor N. Mudge (PACT, 2012)

High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service. - Sudhir Satpathy; Reetuparna Das; Ronald G. Dreslinski; Trevor N. Mudge; Dennis Sylvester; David T. Blaauw (DAC, 2012)

Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems. - Ronald G. Dreslinski; Korey Sewell; Thomas Manville; Sudhir Satpathy; Nathaniel Ross Pinckney; Geoffrey Blake; Michael Cieslak; Reetuparna Das; Thomas F. Wenisch; Dennis Sylvester; David T. Blaauw; Trevor N. Mudge (Hot Chips Symposium, 2012)

Composite Cores: Pushing Heterogeneity Into a Core. - Andrew Lukefahr; Shruti Padmanabha; Reetuparna Das; Faissal M. Sleiman; Ronald G. Dreslinski; Thomas F. Wenisch; Scott A. Mahlke (MICRO, 2012)

Swizzle-Switch Networks for Many-Core Systems. - Korey Sewell; Ronald G. Dreslinski; Thomas Manville; Sudhir Satpathy; Nathaniel Ross Pinckney; Geoffrey Blake; Michael Cieslak; Reetuparna Das; Thomas F. Wenisch; Dennis Sylvester; David T. Blaauw; Trevor N. Mudge (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Scaling towards kilo-core processors with asymmetric high-radix topologies. - Nilmini Abeyratne; Reetuparna Das; Qingkun Li; Korey Sewell; Bharan Giridhar; Ronald G. Dreslinski; David T. Blaauw; Trevor N. Mudge (HPCA, 2013)

Application-to-core mapping policies to reduce memory system interference in multi-core systems. - Reetuparna Das; Rachata Ausavarungnirun; Onur Mutlu; Akhilesh Kumar; Mani Azimi (HPCA, 2013)

Catnap: energy proportional multiple network-on-chip. - Reetuparna Das; Satish Narayanasamy; Sudhir Satpathy; Ronald G. Dreslinski (ISCA, 2013)

Trace based phase prediction for tightly-coupled heterogeneous cores. - Shruti Padmanabha; Andrew Lukefahr; Reetuparna Das; Scott A. Mahlke (MICRO, 2013)

Heterogeneous microarchitectures trump voltage scaling for low-power cores. - Andrew Lukefahr; Shruti Padmanabha; Reetuparna Das; Ronald G. Dreslinski; Thomas F. Wenisch; Scott A. Mahlke (PACT, 2014)

Quality-of-Service for a High-Radix Switch. - Nilmini Abeyratne; Supreet Jeloka; Yiping Kang; David T. Blaauw; Ronald G. Dreslinski; Reetuparna Das; Trevor N. Mudge (DAC, 2014)

Power-Aware NoCs through Routing and Topology Reconfiguration. - Ritesh Parikh; Reetuparna Das; Valeria Bertacco (DAC, 2014)

VIX: Virtual Input Crossbar for Efficient Switch Allocation. - Supriya Rao; Supreet Jeloka; Reetuparna Das; David T. Blaauw; Ronald G. Dreslinski; Trevor N. Mudge (DAC, 2014)

Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration. - Supreet Jeloka; Reetuparna Das; Ronald G. Dreslinski; Trevor N. Mudge; David T. Blaauw (MICRO, 2014)

Design and Evaluation of Hierarchical Rings with Deflection Routing. - Rachata Ausavarungnirun; Chris Fallin; Xiangyao Yu; Kevin Kai-Wei Chang; Greg Nazario; Reetuparna Das; Gabriel H. Loh; Onur Mutlu (SBAC-PAD, 2014)

Getting in control of your control flow with control-data isolation. - William Arthur; Ben Mehne; Reetuparna Das; Todd M. Austin (CGO, 2015)

Locking down insecure indirection with hardware-based control-data isolation. - William Arthur; Sahil Madeka; Reetuparna Das; Todd M. Austin (MICRO, 2015)

DynaMOS: dynamic schedule migration for heterogeneous cores. - Shruti Padmanabha; Andrew Lukefahr; Reetuparna Das; Scott A. Mahlke (MICRO, 2015)

ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks. - Zelalem Birhanu Aweke; Salessawi Ferede Yitbarek; Rui Qiao 002; Reetuparna Das; Matthew Hicks; Yossi Oren; Todd M. Austin (ASPLOS, 2016)

Exploring specialized near-memory processing for data intensive operations. - Salessawi Ferede Yitbarek; Tao Yang; Reetuparna Das; Todd M. Austin (DATE, 2016)

Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing. - Rachata Ausavarungnirun; Chris Fallin; Xiangyao Yu; Kevin Kai-Wei Chang; Greg Nazario; Reetuparna Das; Gabriel H. Loh; Onur Mutlu (CoRR, 2016)

A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate. - Rachata Ausavarungnirun; Chris Fallin; Xiangyao Yu; Kevin Kai-Wei Chang; Greg Nazario; Reetuparna Das; Gabriel H. Loh; Onur Mutlu (Parallel Comput., 2016)

Exploring Fine-Grained Heterogeneity with Composite Cores. - Andrew Lukefahr; Shruti Padmanabha; Reetuparna Das; Faissal M. Sleiman; Ronald G. Dreslinski; Thomas F. Wenisch; Scott A. Mahlke (IEEE Trans. Computers, 2016)

Cache Automaton: Repurposing Caches for Automata Processing. - Arun Subramaniyan 001; Jingcheng Wang; Ezhil R. M. Balasubramanian; David T. Blaauw; Dennis Sylvester; Reetuparna Das (PACT, 2017)

In-memory Data Flow Processor. - Daichi Fujiki; Scott A. Mahlke; Reetuparna Das (PACT, 2017)

Compute Caches. - Shaizeen Aga; Supreet Jeloka; Arun Subramaniyan 001; Satish Narayanasamy; David T. Blaauw; Reetuparna Das (HPCA, 2017)

Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors. - Salessawi Ferede Yitbarek; Misiker Tadesse Aga; Reetuparna Das; Todd M. Austin (HPCA, 2017)

Parallel Automata Processor. - Arun Subramaniyan 001; Reetuparna Das (ISCA, 2017)

Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism. - Jiecao Yu; Andrew Lukefahr; David J. Palframan; Ganesh S. Dasika; Reetuparna Das; Scott A. Mahlke (ISCA, 2017)

Cache automaton. - Arun Subramaniyan 001; Jingcheng Wang; Ezhil R. M. Balasubramanian; David T. Blaauw; Dennis Sylvester; Reetuparna Das (MICRO, 2017)

Mirage cores: the illusion of many out-of-order cores using in-order hardware. - Shruti Padmanabha; Andrew Lukefahr; Reetuparna Das; Scott A. Mahlke (MICRO, 2017)

Blurring the Lines between Memory and Computation. - Reetuparna Das (IEEE Micro, 2017)

In-Memory Data Parallel Processor. - Daichi Fujiki; Scott A. Mahlke; Reetuparna Das (ASPLOS, 2018)

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. - Charles Eckert; Xiaowei Wang; Jingcheng Wang; Arun Subramaniyan 001; Ravi R. Iyer 001; Dennis Sylvester; David T. Blaauw; Reetuparna Das (ISCA, 2018)

GenAx: A Genome Sequencing Accelerator. - Daichi Fujiki; Arun Subramaniyan 001; Tianjun Zhang; Yu Zeng; Reetuparna Das; David T. Blaauw; Satish Narayanasamy (ISCA, 2018)

ASPEN: A Scalable In-SRAM Architecture for Pushdown Automata. - Kevin Angstadt; Arun Subramaniyan 001; Elaheh Sadredini; Reza Rahimi; Kevin Skadron; Westley Weimer; Reetuparna Das (MICRO, 2018)

Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks. - Xiaowei Wang; Jiecao Yu; Charles Augustine; Ravi R. Iyer 001; Reetuparna Das (HPCA, 2019)

Duality cache for data parallel acceleration. - Daichi Fujiki; Scott A. Mahlke; Reetuparna Das (ISCA, 2019)

A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration. - Jingcheng Wang; Xiaowei Wang; Charles Eckert; Arun Subramaniyan 001; Reetuparna Das; David T. Blaauw; Dennis Sylvester (ISSCC, 2019)

Compute cache for data parallel acceleration. - Reetu Das (NoCArc@MICRO, 2019)

TF-Net: Deploying Sub-Byte Deep Neural Networks on Microcontrollers. - Jiecao Yu; Andrew Lukefahr; Reetuparna Das; Scott A. Mahlke (ACM Trans. Embed. Comput. Syst., 2019)

MARTINI: Memory Access Traces to Detect Attacks. - Yujun Qin; Samuel Gonzalez; Kevin Angstadt; Xiaowei Wang; Stephanie Forrest; Reetuparna Das; Kevin Leach; Westley Weimer (CCSW, 2020)

A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array. - Zhehong Wang; Tianjun Zhang; Daichi Fujiki; Arun Subramaniyan 001; Xiao Wu 002; Makoto Yasuda; Satoru Miyoshi; Masaru Kawaminami; Reetuparna Das; Satish Narayanasamy; David T. Blaauw (CICC, 2020)

Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning. - Vidushi Goyal; Valeria Bertacco; Reetuparna Das (DAC, 2020)

Neksus: An Interconnect for Heterogeneous System-In-Package Architectures. - Vidushi Goyal; Xiaowei Wang; Valeria Bertacco; Reetuparna Das (IPDPS, 2020)

SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space. - Daichi Fujiki; Shunhao Wu; Nathan Ozog; Kush Goliya; David T. Blaauw; Satish Narayanasamy; Reetuparna Das (MICRO, 2020)

17.3 GCUPS Pruning-Based Pair-Hidden-Markov-Model Accelerator for Next-Generation DNA Sequencing. - Xiao Wu 002; Arun Subramaniyan 001; Zhehong Wang; Satish Narayanasamy; Reetu Das; David T. Blaauw (VLSI Circuits, 2020)

A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing. - Jingcheng Wang; Xiaowei Wang; Charles Eckert; Arun Subramaniyan 001; Reetuparna Das; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2020)

MyML: User-Driven Machine Learning. - Vidushi Goyal; Valeria Bertacco; Reetuparna Das (DAC, 2021)

Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. - Xiaowei Wang; Vidushi Goyal; Jiecao Yu; Valeria Bertacco; Andrew Boutros; Eriko Nurvitadhi; Charles Augustine; Ravi R. Iyer 001; Reetuparna Das (FCCM, 2021)

Accelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees. - Arun Subramaniyan 001; Jack Wadden; Kush Goliya; Nathan Ozog; Xiao Wu 002; Satish Narayanasamy; David T. Blaauw; Reetuparna Das (ISCA, 2021)

GenomicsBench: A Benchmark Suite for Genomics. - Arun Subramaniyan 001; Yufeng Gu; Timothy Dunn; Somnath Paul; Md. Vasimuddin; Sanchit Misra; David T. Blaauw; Satish Narayanasamy; Reetuparna Das (ISPASS, 2021)

SquiggleFilter: An Accelerator for Portable Virus Detection. - Timothy Dunn; Harisankar Sadasivan; Jack Wadden; Kush Goliya; Kuan-Yu Chen 001; David T. Blaauw; Reetuparna Das; Satish Narayanasamy (MICRO, 2021)

Cache Compression with Efficient in-SRAM Data Comparison. - Xiaowei Wang; Charles Augustine; Eriko Nurvitadhi; Ravi R. Iyer 001; Li Zhao 002; Reetuparna Das (NAS, 2021)

A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array. - Zhehong Wang; Tianjun Zhang; Daichi Fujiki; Arun Subramaniyan 001; Xiao Wu 002; Makoto Yasuda; Satoru Miyoshi; Masaru Kawaminami; Reetuparna Das; Satish Narayanasamy; David T. Blaauw (IEEE J. Solid State Circuits, 2021)

In-/Near-Memory Computing - Daichi Fujiki; Xiaowei Wang; Arun Subramaniyan 001; Reetuparna Das (Morgan & Claypool Publishers, 2021)

Multi-Layer In-Memory Processing. - Daichi Fujiki; Alireza Khadem; Scott A. Mahlke; Reetuparna Das (MICRO, 2022)

Special Issue on In-Memory Computing. - Reetuparna Das (IEEE Micro, 2022)

Hardware-friendly User-specific Machine Learning for Edge Devices. - Vidushi Goyal; Reetuparna Das; Valeria Bertacco (ACM Trans. Embed. Comput. Syst., 2022)

Vector-Processing for Mobile Devices: Benchmark and Analysis. - Alireza Khadem; Daichi Fujiki; Nishil Talati; Scott A. Mahlke; Reetuparna Das (IISWC, 2023)

GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis. - Yufeng Gu; Arun Subramaniyan 001; Timothy Dunn; Alireza Khadem; Kuan-Yu Chen 001; Somnath Paul; Md. Vasimuddin; Sanchit Misra; David T. Blaauw; Satish Narayanasamy; Reetuparna Das (ISCA, 2023)

Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks. - Charles Eckert; Arun Subramaniyan 001; Xiaowei Wang; Charles Augustine; Ravishankar Iyer 001; Reetuparna Das (IEEE Trans. Computers, 2023)

BitSET: Bit-Serial Early Termination for Computation Reduction in Convolutional Neural Networks. - Yunjie Pan; Jiecao Yu; Andrew Lukefahr; Reetuparna Das; Scott A. Mahlke (ACM Trans. Embed. Comput. Syst., 2023)

nPoRe: n-polymer realigner for improved pileup-based variant calling. - Timothy Dunn; David T. Blaauw; Reetuparna Das; Satish Narayanasamy (BMC Bioinform., 2023)

Duet: A Collaborative User Driven Recommendation System for Edge Devices. - Vidushi Goyal; Valeria Bertacco; Reetuparna Das (DAC, 2024)

Systems Challenges and Opportunities for Genomics. - Reetuparna Das; Satish Narayanasamy (Computer, 2024)

PIM Is All You Need: A CXL-Enabled GPU-Free System for Large Language Model Inference. - Yufeng Gu; Alireza Khadem; Sumanth Umesh; Ning Liang; Xavier Servot; Onur Mutlu; Ravi R. Iyer 001; Reetuparna Das (ASPLOS (2), 2025)

Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing. - Alireza Khadem; Daichi Fujiki; Hilbert Chen; Yufeng Gu; Nishil Talati; Scott A. Mahlke; Reetuparna Das (HPCA, 2025)

DX100: Programmable Data Access Accelerator for Indirection. - Alireza Khadem; Kamalavasan Kamalakkannan; Zhenyan Zhu; Akash Poptani; Yufeng Gu; Jered Benjamin Dominguez-Trujillo; Nishil Talati; Daichi Fujiki; Scott A. Mahlke; Galen M. Shipman; Reetuparna Das (ISCA, 2025)

Characterizing Adaptive Mesh Refinement on Heterogeneous Platforms with Parthenon-VIBE. - Akash Poptani; Alireza Khadem; Scott A. Mahlke; Jonah M. Miller; Joshua C. Dolence; Reetuparna Das (CoRR, 2025)