According to our database1, Régis Roubadia authored at least 2 papers between 2006 and 2007.
Legend:Book In proceedings Article PhD thesis Other
Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006