Régis Roubadia

According to our database, Régis Roubadia authored at least 2 papers between 2006 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2007

Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology.

Régis Roubadia, Sami Ajram, Guy Cathébras

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs.

Régis Roubadia, Sami Ajram, Guy Cathébras

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006