Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs. - Régis Roubadia; Sami Ajram; Guy Cathébras (PATMOS, 2006)

Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology. - Régis Roubadia; Sami Ajram; Guy Cathébras (ISCAS, 2007)