A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. - Rei-Fu Huang; Jin-Fu Li 001; Jen-Chieh Yeh; Cheng-Wen Wu (IOLTW, 2002)

A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. - Rei-Fu Huang; Jin-Fu Li 001; Jen-Chieh Yeh; Cheng-Wen Wu (MTDT, 2002)

Defect Oriented Fault Analysis for SRAM. - Rei-Fu Huang; Yung-Fa Chou; Cheng-Wen Wu (Asian Test Symposium, 2003)

A Processor-Based Built-In Self-Repair Design for Embedded Memories. - Chin-Lung Su; Rei-Fu Huang; Cheng-Wen Wu (Asian Test Symposium, 2003)

A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. - Jin-Fu Li 001; Jen-Chieh Yeh; Rei-Fu Huang; Cheng-Wen Wu; Peir-Yuan Tsai; Archer Hsu; Eugene Chow (ITC, 2003)

A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. - Rei-Fu Huang; Li-Ming Denq; Cheng-Wen Wu; Jin-Fu Li 001 (MTDT, 2003)

SRAM delay fault modeling and test algorithm development. - Rei-Fu Huang; Yan-Ting Lai; Yung-Fa Chou; Cheng-Wen Wu (ASP-DAC, 2004)

Fail Pattern Identification for Memory Built-In Self-Repair. - Rei-Fu Huang; Chin-Lung Su; Cheng-Wen Wu; Shen-Tien Lin; Kun-Lun Luo; Yeong-Jar Chang (Asian Test Symposium, 2004)

On Test and Diagnostics of Flash Memories. - Chih-Tsun Huang; Jen-Chieh Yeh; Yuan-Yuan Shih; Rei-Fu Huang; Cheng-Wen Wu (Asian Test Symposium, 2004)

MRAM Defect Analysis and Fault Modeli. - Chin-Lung Su; Rei-Fu Huang; Cheng-Wen Wu; Chien-Chung Hung; Ming-Jer Kao; Yeong-Jar Chang; Wen Ching Wu (ITC, 2004)

A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. - Li-Ming Denq; Rei-Fu Huang; Cheng-Wen Wu; Yeong-Jar Chang; Wen Ching Wu (MTDT, 2004)

A built-in self-repair design for RAMs with 2-D redundancy. - Jin-Fu Li 001; Jen-Chieh Yeh; Rei-Fu Huang; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Economic Aspects of Memory Built-in Self-Repair. - Rei-Fu Huang; Chao-Hsun Chen; Cheng-Wen Wu (IEEE Des. Test Comput., 2007)

Raisin: Redundancy Analysis Algorithm Simulation. - Rei-Fu Huang; Jin-Fu Li 001; Jen-Chieh Yeh; Cheng-Wen Wu (IEEE Des. Test Comput., 2007)

Testing Methodology of Embedded DRAMs. - Chi-Min Chang; Mango Chia-Tso Chao; Rei-Fu Huang; Ding-Yuan Chen (ITC, 2008)

Fault models for embedded-DRAM macros. - Mango Chia-Tso Chao; Hao-Yu Yang; Rei-Fu Huang; Shih-Chin Lin; Ching-Yu Chin (DAC, 2009)

Fault models and test methods for subthreshold SRAMs. - Chen-Wei Lin; Hung-Hsin Chen; Hao-Yu Yang; Mango Chia-Tso Chao; Rei-Fu Huang (ITC, 2010)

A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories. - Chin-Lung Su; Rei-Fu Huang; Cheng-Wen Wu; Kun-Lun Luo; Wen Ching Wu (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Alternate hammering test for application-specific DRAMs and an industrial case study. - Rei-Fu Huang; Hao-Yu Yang; Mango Chia-Tso Chao; Shih-Chin Lin (DAC, 2012)

Testing Methodology of Embedded DRAMs. - Hao-Yu Yang; Chi-Min Chang; Mango Chia-Tso Chao; Rei-Fu Huang; Shih-Chin Lin (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Fault Models and Test Methods for Subthreshold SRAMs. - Chen-Wei Lin; Hung-Hsin Chen; Hao-Yu Yang; Chin-Yuan Huang; Mango Chia-Tso Chao; Rei-Fu Huang (IEEE Trans. Computers, 2013)

Testing methods for a write-assist disturbance-free dual-port SRAM. - Hao-Yu Yang; Chen-Wei Lin; Chao-Ying Huang; Ching-Ho Lu; Chen-An Lai; Mango Chia-Tso Chao; Rei-Fu Huang (VTS, 2014)

Testing methods for quaternary content addressable memory using charge-sharing sensing scheme. - Hao-Yu Yang; Rei-Fu Huang; Chin-Lung Su; Kuan-Hong Lin; Hang-Kaung Shu; Chi-Wei Peng; Mango Chia-Tso Chao (ITC, 2015)