An effective delay analysis system for a large scale computer design. - Reiji Toyoshima; Yoshimitsu Takiguchi; Kazumi Matsumoto; Hidetomo Hongou; Mashiro Hashimoto; Ryotaro Kamikawai; Katsuhiko Takizawa (DAC, 1986)

Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design. - Yasushi Ogawa; Tsutomu Itoh; Yoshio Miki; Tatsuki Ishii; Yasuo Sato; Reiji Toyoshima (DAC, 1991)