Hierarchical power distribution and power management scheme for a single chip mobile processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (DAC, 2006)

A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (ISSCC, 2006)

A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS. - Masayuki Ito; Toshihiro Hattori; Takahiro Irita; Ken Tatezawa; Fumihito Tanaka; Kenji Hirose; Shinichi Yoshioka; Koji Ohno; Reiko Tsuchihashi; Minoru Sakata; Masayuki Yamamoto; Yuji Aral (ISSCC, 2007)