SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. - Jonghee W. Yoon; Aviral Shrivastava; Sanghyun Park; Minwook Ahn; Reiley Jeyapaul; Yunheung Paek (ASP-DAC, 2008)

Code Transformations for TLB Power Reduction. - Reiley Jeyapaul; Sandeep Marathe; Aviral Shrivastava (VLSI Design, 2009)

Cache vulnerability equations for protecting data in embedded processor caches from soft errors. - Aviral Shrivastava; Jongeun Lee; Reiley Jeyapaul (LCTES, 2010)

B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems. - Reiley Jeyapaul; Aviral Shrivastava (SCOPES, 2010)

Code Transformations for TLB Power Reduction. - Reiley Jeyapaul; Aviral Shrivastava (Int. J. Parallel Program., 2010)

Smart cache cleaning: energy efficient vulnerability reduction in embedded processors. - Reiley Jeyapaul; Aviral Shrivastava (CASES, 2011)

UnSync: A Soft Error Resilient Redundant Multicore Architecture. - Reiley Jeyapaul; Fei Hong; Abhishek Rhisheekesan; Aviral Shrivastava; Kyoungwoo Lee (ICPP, 2011)

Enabling Multithreading on CGRAs. - Aviral Shrivastava; Jared Pager; Reiley Jeyapaul; Mahdi Hamzeh; Sarma B. K. Vrudhula (ICPP, 2011)

Soft errors: the hardware-software interface. - Kyoungwoo Lee; Aviral Shrivastava; Reiley Jeyapaul (CODES+ISSS, 2012)

Enabling energy efficient reliability in embedded systems through smart cache cleaning. - Reiley Jeyapaul; Aviral Shrivastava (ACM Trans. Design Autom. Electr. Syst., 2013)

Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors. - Aviral Shrivastava; Abhishek Rhisheekesan; Reiley Jeyapaul; Carole-Jean Wu (DAC, 2014)

UnSync-CMP: Multicore CMP Architecture for Energy-Efficient Soft-Error Reliability. - Reiley Jeyapaul; Fei Hong; Abhishek Rhisheekesan; Aviral Shrivastava; Kyoungwoo Lee (IEEE Trans. Parallel Distributed Syst., 2014)

Guidelines to design parity protected write-back L1 data cache. - Yohan Ko; Reiley Jeyapaul; Youngbin Kim; Kyoungwoo Lee; Aviral Shrivastava (DAC, 2015)

A Software Scheme for Multithreading on CGRAs. - Jared Pager; Reiley Jeyapaul; Aviral Shrivastava (ACM Trans. Embed. Comput. Syst., 2015)

gemV: A validated toolset for the early exploration of system reliability. - Karthik Tanikella; Yohan Ko; Reiley Jeyapaul; Kyoungwoo Lee; Aviral Shrivastava (ASAP, 2016)

Protecting Caches from Soft Errors: A Microarchitect's Perspective. - Yohan Ko; Reiley Jeyapaul; Youngbin Kim; Kyoungwoo Lee; Aviral Shrivastava (ACM Trans. Embed. Comput. Syst., 2017)

Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability. - Reiley Jeyapaul; Roberto Flores; Alfonso Ávila 001; Aviral Shrivastava (IEEE Trans. Very Large Scale Integr. Syst., 2017)

LASER: A hardware/software approach to accelerate complicated loops on CGRAs. - Mahesh Balasubramanian 001; Shail Dave; Aviral Shrivastava; Reiley Jeyapaul (DATE, 2018)

Control Flow Checking or Not? (for Soft Errors). - Abhishek Rhisheekesan; Reiley Jeyapaul; Aviral Shrivastava (ACM Trans. Embed. Comput. Syst., 2019)

The gem5 Simulator: Version 20.0+. - Jason Lowe-Power; Abdul Mutaal Ahmad; Ayaz Akram; Mohammad Alian; Rico Amslinger; Matteo Andreozzi; Adrià Armejach; Nils Asmussen; Srikant Bharadwaj; Gabe Black; Gedare Bloom; Bobby R. Bruce; et al. (CoRR, 2020)

Characterizing Soft-Error Resiliency in Arm's Ethos-U55 Embedded Machine Learning Accelerator. - Abhishek Tyagi; Reiley Jeyapaul; Chuteng Zhou; Paul N. Whatmough; Yuhao Zhu 001 (ISPASS, 2024)

Characterizing Soft-Error Resiliency in Arm's Ethos-U55 Embedded Machine Learning Accelerator. - Abhishek Tyagi; Reiley Jeyapaul; Chuteng Zhu; Paul N. Whatmough; Yuhao Zhu 001 (CoRR, 2024)