Where-Oblivious is not Sufficient. - Reiner Kolla (Inf. Process. Lett., 1983)

On Network Algebras and Recursive Equations. - Günter Hotz; Reiner Kolla; Paul Molitor (Graph-Grammars and Their Application to Computer Science, 1986)

Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I. - Günter Hotz; Bernd Becker 001; Reiner Kolla; Paul Molitor (Inform. Forsch. Entwickl., 1986)

Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II. - Günter Hotz; Bernd Becker 001; Reiner Kolla; Paul Molitor (Inform. Forsch. Entwickl., 1986)

Hierarchical Design Based on a Calculus of Nets. - Bernd Becker 001; Günter Hotz; Reiner Kolla; Paul Molitor; Hans-Georg Osthof (DAC, 1987)

Spezifikation und Expansion logisch-topologischer Netze. - Reiner Kolla (1987)

On the Construction of Optimal Time Adders (Extended Abstract). - Bernd Becker 001; Reiner Kolla (STACS, 1988)

Einführung in den VLSI-Entwurf. - Reiner Kolla; Paul Molitor; Hans-Georg Osthof (Teubner, 1989)

A note on hierarchical layer-assignment. - Reiner Kolla; Paul Molitor (Integr., 1989)

A graphical system for hierarchical specifications and checkups of VLSI circuits. - Bernd Becker 001; Thomas Burch; Günter Hotz; D. Kiel; Reiner Kolla; Paul Molitor; Hans-Georg Osthof; Gisela Pitsch; Uwe Sparmann (EURO-DAC, 1990)

Cell based performance optimization of combinational circuits. - Uwe Hinsberger; Reiner Kolla (EURO-DAC, 1990)

A dynamic programming approach to the power supply net sizing problem. - Reiner Kolla (EURO-DAC, 1990)

Minimal Area Sizing of Power Supply Nets in VLSI Circuits. - Reiner Kolla (J. Inf. Process. Cybern., 1990)

The Virtual Feedback Problem in Hierarchical Representations of Combinational Circuits. - Reiner Kolla; Bernd Serf (Acta Informatica, 1991)

Performance Optimization of Combinational Circuits. - Uwe Hinsberger; Reiner Kolla (Informatik, 1992)

A cell-based approach to performance optimization of fanout-free circuits. - Uwe Hinsberger; Reiner Kolla (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Optimal technology mapping for single output cells. - Uwe Hinsberger; Reiner Kolla (Great Lakes Symposium on VLSI, 1995)

TROY: A Tree-Based Approach to Logic Synthesis and Technology Mapping. - Winfried Nöth; Uwe Hinsberger; Reiner Kolla (Great Lakes Symposium on VLSI, 1996)

A parallel hybrid approach to hard optimization problems. - Uwe Hinsberger; Reiner Kolla; Markus Wild (ARCS, 1997)

Node normalization and decomposition in low power technology mapping. - Winfried Nöth; Reiner Kolla (ISLPED, 1997)

Boolean Matching for Large Libraries. - Uwe Hinsberger; Reiner Kolla (DAC, 1998)

PACE: Processor Architectures for Circuit Emulation. - Reiner Kolla; Oliver Springauf (IPPS/SPDP Workshops, 1998)

Splitting Double Precision FPUs for Single Precision Interval Arithmetic. - Reiner Kolla; A. Vodopivec; Jürgen Wolff von Gudenberg (ARCS Workshops, 1999)

Spanning Tree-based State Encoding for Low Power Dissipation. - Winfried Nöth; Reiner Kolla (DATE, 1999)

A New Floorplanning Method for FPGA Architectural Research. - Frank Wolz; Reiner Kolla (FPL, 2000)

Technology Binding. - Reiner Kolla (Inform. Spektrum, 2000)

Bubble Partitioning for LUT-Based Sequential Circuits. - Frank Wolz; Reiner Kolla (FPL, 2001)

A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures. - Frank Wolz; Reiner Kolla (FPL, 2002)

Disproving the Perfect-Rate Property of Data-Flow Graphs Unfolded by the Least Common Multiple of the Number of Loop Registers. - Frank Wolz; Reiner Kolla (IEEE Trans. Computers, 2003)

A Method for Self-Organizing Communication in WSN Based Localization Systems: HashSlot. - Marcel Baunach; Reiner Kolla; Clemens Muhlberger (LCN, 2007)

Beyond Theory: Development of a Real World Localization Application as Low Power WSN. - Marcel Baunach; Reiner Kolla; Clemens Muhlberger (LCN, 2007)

Precise self-calibration of ultrasound based indoor localization systems. - Armin Runge; Marcel Baunach; Reiner Kolla (IPIN, 2011)

An Alternating Transmission Scheme for Deflection Routing Based Network-on-Chips. - Armin Runge; Reiner Kolla (ARCS, 2016)

A wearable 1-lead necklace ECG for continuous heart rate monitoring. - Aulia Arif Iskandar; Reiner Kolla; Klaus Schilling 001; Wolfram Völker (HealthCom, 2016)

Consideration of the Flit Size for Deflection Routing based Network-on-Chips. - Armin Runge; Reiner Kolla (AISTECS@HiPEAC, 2016)

Using benes networks at fault-tolerant and deflection routing based network-on-chips. - Armin Runge; Reiner Kolla (NOCS, 2016)

MCGC: A Network Coding Approach for Reliable Large-scale Wireless Networks. - Isabel Madeleine Runge; Reiner Kolla (FAILSAFE@SenSys, 2017)

TwoPhases: A transmission scheme to reduce the link width at deflection routing based Network-on-Chips. - Armin Runge; Reiner Kolla (J. Syst. Archit., 2017)