Suchlistenstrukturen zur Darstellung gerichteter Graphen und deren Anwendung bei Synthese und Minimierung spezieller endlicher Automaten. - Reiner W. Hartenstein (Elektron. Rechenanlagen, 1970)

Synthese endlicher Automaten bei Problemen der Erkennung, Klassifikation und Informationsreduktion. - Reiner W. Hartenstein (J. Inf. Process. Cybern., 1971)

Experimentiersystem für ein technisches Informatikpraktikum. - Reiner W. Hartenstein (GI Jahrestagung, 1972)

Hierarchy of Interpreters for Modelling Complex Digital Systems. - Reiner W. Hartenstein (GI Jahrestagung, 1973)

Increasing Hardware Complexity - A Challenge to Computer Architecture Education. - Reiner W. Hartenstein (ISCA, 1973)

A microprogrammable display processor concept. - Reiner W. Hartenstein; Klaus D. Mueller (MICRO, 1973)

Konzepte der Mikroprogrammierung. - Reiner W. Hartenstein (ARCS, 1974)

Microprogramming concepts - a step towards structured hardware design. - Reiner W. Hartenstein (MICRO, 1974)

Letter to membership from incoming chairman (CAN, Oct. 73). - Reiner W. Hartenstein (SIGARCH Comput. Archit. News, 1974)

Fundamentals of Structured Hardware Design. - Reiner W. Hartenstein (North-Holland, 1977)

Software-Zuverlässigkeit mit Rechnernetz-Baukästen verteilter Programmierung. - J. Dieckmann; Reiner W. Hartenstein; Werner Konrad (Hardware für Software, 1980)

Ein Compiler für die Register Transfer-Sprache KARL-2. - Reiner W. Hartenstein; Peter Liell (GI Jahrestagung, 1980)

VLSI-Bausteine in geringen Stückzahlen für Spezial-Anwendungen. - Reiner W. Hartenstein (Elektron. Rechenanlagen, 1980)

VLSI-Algorithmen - Das aktuelle Schlagwort. - Reiner W. Hartenstein (Inform. Spektrum, 1981)

Die "Neue Mikroelektronik" in der Informatik: Voraussetzungen und Auswirkungen. - Reiner W. Hartenstein (GI Jahrestagung, 1982)

KARL-II - eine Sprache zur Spezifikation beim Entwurf Kundenspezifischer Digitalbausteine. - Reiner W. Hartenstein (Angew. Inform., 1982)

Silicon Compiler - Das aktuelle Schlagwort. - Reiner W. Hartenstein (Inform. Spektrum, 1983)

Mehrebenenen-Graphik-Editor MLED als DBMS für VLSI-Simulation. - Reiner W. Hartenstein; Udo Welters (Simulationstechnik, 1987)

A flexible architecture for image processing. - Reiner W. Hartenstein; Alexander G. Hirschbiel; Michael Weber 008 (Microprocess. Microprogramming, 1987)

MLED: A multiple abstraction level graphical editor. - Reiner W. Hartenstein; Udo Welters (Microprocess. Microprogramming, 1987)

MLED - Ein Mehrebenen Graphik Editor für den VLSI-Entwurf. - Reiner W. Hartenstein; K. W. Jörg; Udo Welters (GI Jahrestagung (2), 1988)

Partitionierungsschemata für Rechnerstrukturen. - Reiner W. Hartenstein; Michael Ryba (GI Jahrestagung (2), 1988)

The KARL/KARATE system - integrating functional test development into a CAD environment for VLSI. - Gerold Alfs; Reiner W. Hartenstein; Andrea Wodtko (ICCD, 1988)

The KARL/KARATE System: Automatic Test Pattern Generation Based on RT Level Descriptions. - Gerold Affs; Reiner W. Hartenstein; Andrea Wodtko (ITC, 1988)

A technology description method for generalized layout / circuit relations. - Joachim Blödel; Reiner W. Hartenstein; Wolfgang Nebel; Michael Ryba (Microprocess. Microprogramming, 1988)

Microelectronics: VLSI design tools I. - Reiner W. Hartenstein (Microprocess. Microprogramming, 1988)

Explicit fault modeling and hierarchical test pattern generation in the KARATE system. - Gerold Alfs; Reiner W. Hartenstein; Andrea Wodtko (Microprocessing and Microprogramming, 1989)

Synthesis of systolic architectures using the SYS3 system. - Reiner W. Hartenstein; Karin Lemmert; Michael Riedmüller (Microprocessing and Microprogramming, 1989)

Xputers: An Open Family of Non-Von Neumann Architectures. - Reiner W. Hartenstein; Alexander G. Hirschbiel; Michael Weber 008 (ARCS, 1990)

A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware. - Reiner W. Hartenstein; Alexander G. Hirschbiel; Michael Weber 008 (CONPAR, 1990)

Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image Processing. - Reiner W. Hartenstein; Alexander G. Hirschbiel; Michael Riedmüller; Karin Schmidt; Michael Weber 008 (DAGM-Symposium, 1990)

The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration. - Reiner W. Hartenstein; Alexander G. Hirschbiel; Michael Weber 008 (ICPP (1), 1990)

Xputers: very high throughput by innovative computing principles. - Reiner W. Hartenstein; Alexander G. Hirschbiel; Michael Weber 008 (Jerusalem Conference on Information Technology, 1990)

Xputer use in image processing and digital signal processing. - Reiner W. Hartenstein; Alexander G. Hirschbiel; Karin Lemmert; Michael Riedmüller; Karin Schmidt; Michael Weber 008 (VCIP, 1990)

Gemeinsame Stellungnahme der Fakultätentage Elektrotechnik und Informatik zur Abstimmung ihrer Fachgebierte im Bereich Informationstechnik. - Franz-Josef Brandenburg; Werner Freise; Winfried Görke; Reiner W. Hartenstein; P. Kühn; H. J. Schmitt (Inform. Spektrum, 1991)

A novel ASIC design approach based on a new machine paradigm. - Reiner W. Hartenstein; Alexander G. Hirschbiel; Michael Riedmüller; Karin Schmidt; Michael Weber 008 (IEEE J. Solid State Circuits, 1991)

Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. - Andreas Ast; Reiner W. Hartenstein; Rainer Kress 002; Helmut Reinig; Karin Schmidt (FPL, 1992)

An Information Model Describing the Exchange of IC Technology Data. - Joachim Blödel; Markus Brandstetter; Peter Conradi; Walter Drangmeister; Reiner W. Hartenstein; Dietmar Schroeder (Electronic Design Automation Frameworks, 1992)

A novel paradigm of parallel computation and its use to implement simple high-performance hardware. - Reiner W. Hartenstein; Alexander G. Hirschbiel; Karin Schmidt; Michael Weber 008 (Future Gener. Comput. Syst., 1992)

CMOS interconnect modelling for timing analysis. - Rainer Kress 002; Elmar U. K. Melcher; Reiner W. Hartenstein; Michel Dana (Microprocess. Microprogramming, 1993)

Wozu noch Mikro-Chips? - Einführung in Methoden der Technischen Informatik zur Anwendung der Mikroelektronik für die Wettbewerbsfähigkeit unserer Wirtschaft: Sachbuch und Textbuch. - Reiner W. Hartenstein (IT Press, 1994)

A dynamically reconfigurable wavefront array architecture for evaluation of expressions. - Reiner W. Hartenstein; Rainer Kress 002; Helmut Reinig (ASAP, 1994)

Data-Procedural Languages for FPL-based Machines. - Andreas Ast; Jürgen Becker 001; Reiner W. Hartenstein; Rainer Kress 002; Helmut Reinig; Karin Schmidt (FPL, 1994)

A New FPGA Architecture for Word-Oriented Datapaths. - Reiner W. Hartenstein; Rainer Kress 002; Helmut Reinig (FPL, 1994)

A Parallelizing Compilation Method for the Map-oriented Machine. - Reiner W. Hartenstein; Jürgen Becker 001; Rainer Kress 002; Helmut Reinig; Karin Schmidt (ASAP, 1995)

A datapath synthesis system for the reconfigurable datapath architecture. - Reiner W. Hartenstein; Rainer Kress 002 (ASP-DAC, 1995)

Combining structural and procedural programming by parallelizing compilation. - Reiner W. Hartenstein; Karin Schmidt (SAC, 1995)

Hardware/Software Co-Design - Das aktuelle Schlagwort - Reiner W. Hartenstein (Inform. Spektrum, 1995)

Custom Computing Machines - Das aktuelle Schlagwort - Reiner W. Hartenstein (Inform. Spektrum, 1995)

Null Bock auf High Tech - Arbeitsplatz-Export: nur weil die Löhne zu hoch sind? - Reiner W. Hartenstein (IT Press, 1996)

A Synthesis System For Bus-Based Wavefront Array Architectures. - Reiner W. Hartenstein; Jürgen Becker 001; Michael Herz; Rainer Kress 002; Ulrich Nageldinger (ASAP, 1996)

Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. - Reiner W. Hartenstein; Jürgen Becker 001; Rainer Kress 002 (CODES, 1996)

Two-Level Hardware/Software Partitioning Using CoDe-X. - Reiner W. Hartenstein; Jürgen Becker 001; Rainer Kress 002 (ECBS, 1996)

An Embedded Accelerator for Real-Time Image Processing. - Reiner W. Hartenstein; Jürgen Becker 001; Rainer Kress 002 (RTS, 1996)

Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. - Reiner W. Hartenstein; Jürgen Becker 001; Rainer Kress 002 (FPL, 1996)

A Partitioning Programming Environment for a Novel Parallel Architecture. - Reiner W. Hartenstein; Jürgen Becker 001; Michael Herz; Rainer Kress 002; Ulrich Nageldinger (IPPS, 1996)

CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. - Reiner W. Hartenstein; Jürgen Becker 001; Rainer Kress 002; Helmut Reinig (VLSI Design, 1996)

High-performance computing using a reconfigurable accelerator. - Reiner W. Hartenstein; Jürgen Becker 001; Rainer Kress 002; Helmut Reinig (Concurr. Pract. Exp., 1996)

A Novel Universal Sequencer Hardware. - Reiner W. Hartenstein; Jürgen Becker 001; Michael Herz; Ulrich Nageldinger (ARCS, 1997)

A Novel Sequencer Hardware for Application Specific Computing. - Reiner W. Hartenstein; Jürgen Becker 001; Michael Herz; Ulrich Nageldinger (ASAP, 1997)

Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. - Reiner W. Hartenstein; Jürgen Becker 001 (CODES, 1997)

Data scheduling to increase performance of parallel accelerators. - Reiner W. Hartenstein; Jürgen Becker 001; Michael Herz; Ulrich Nageldinger (FPL, 1997)

An operating system for custom computing machines based on the Xputer paradigm. - Rainer Kress 002; Reiner W. Hartenstein; Ulrich Nageldinger (FPL, 1997)

A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. - Reiner W. Hartenstein; Jürgen Becker 001 (HICSS (5), 1997)

Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. - Reiner W. Hartenstein; Jürgen Becker 001 (VLSI Design, 1997)

Seeking Solutions in Configurable Computing. - William H. Mangione-Smith; Brad Hutchins; David L. Andrews 001; André DeHon; Carl Ebeling; Reiner W. Hartenstein; Oskar Mencer; John Morris; Krishna V. Palem; Viktor K. Prasanna; Henk A. E. Spaanenburg (Computer, 1997)

Parallelization in Co-Compilation for Configurable Accelerators. - Jürgen Becker 001; Reiner W. Hartenstein; Michael Herz; Ulrich Nageldinger (ASP-DAC, 1998)

Designing for Xilinx XC6200 FPGAs. - Reiner W. Hartenstein; Michael Herz; Frank Gilbert (FPL, 1998)

Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators. - Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger (FPL, 1998)

Introduction to the Configware Minitrack: Hardware and Software Come Closer. - Reiner W. Hartenstein (HICSS (7), 1998)

On Reconfigurable Co-processing Units. - Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger (IPPS/SPDP Workshops, 1998)

Real-Time Prototyping in Microprocessor/Accelerator Symbiosis. - Jürgen Becker 001; Reiner W. Hartenstein (International Workshop on Rapid System Prototyping, 1998)

Mapping Applications onto Reconfigurable Kress Arrays. - Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger (FPL, 1999)

An Internet Based Development Framework for Reconfigurable Computing. - Reiner W. Hartenstein; Michael Herz; Ulrich Nageldinger; Thomas Hoffmann 001 (FPL, 1999)

Configware: From Glue Logic Synthesis to Reconfigurable Computing Systems- Introduction. - Reiner W. Hartenstein; Veljko M. Milutinovic (HICSS, 1999)

KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. - Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger (ASP-DAC, 2000)

Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract). - Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger (FPGA, 2000)

Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. - Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger (FPL, 2000)

Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. - Reiner W. Hartenstein; Thomas Hoffmann 001; Ulrich Nageldinger (PATMOS, 2000)

Coarse grain reconfigurable architecture (embedded tutorial). - Reiner W. Hartenstein (ASP-DAC, 2001)

A decade of reconfigurable computing: a visionary retrospective. - Reiner W. Hartenstein (DATE, 2001)

Reconfigurable Computing: A New Business Model and its Impact on SoC Design. - Reiner W. Hartenstein (DSD, 2001)

Disruptive Trends by Data-Stream-Based Computing. - Reiner W. Hartenstein (FPL, 2002)

Trends in reconfigurable logic and reconfigurable computing. - Reiner W. Hartenstein (ICECS, 2002)

Memory addressing organization for stream-based reconfigurable computing. - Michael Herz; Reiner W. Hartenstein; Miguel Miranda; Erik Brockmeyer; Francky Catthoor (ICECS, 2002)

Applying ELAN Strategies in Simulating Processors over Simple Architectures. - Mauricio Ayala-Rincón; Rinaldi Maya Neto; Ricardo P. Jacobi; Carlos H. Llanos; Reiner W. Hartenstein (WRS, 2002)

Architectural Specification, Exploration and Simulation Through Rewriting-Logic. - Mauricio Ayala-Rincón; Reiner W. Hartenstein; Rinaldi Maya Neto; Ricardo P. Jacobi; Carlos H. Llanos (Rev. Colomb. de Computación, 2002)

Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing. - Mauricio Ayala-Rincón; Ricardo P. Jacobi; Carlos H. Llanos; Reiner W. Hartenstein (FDL, 2003)

Are We Really Ready for the Breakthrough? - Reiner W. Hartenstein (IPDPS, 2003)

Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic. - Mauricio Ayala-Rincón; Rodrigo Borges Nogueira; Carlos H. Llanos; Ricardo P. Jacobi; Reiner W. Hartenstein (SBCCI, 2003)

Efficient Computation of Algebraic Operations over Dynamically Reconfigurable Systems Specified by Rewriting-Logic Environments. - Mauricio Ayala-Rincón; Rodrigo Borges Nogueira; Carlos H. Llanos; Ricardo P. Jacobi; Reiner W. Hartenstein (SCCC, 2003)

Configware and morphware going mainstream. - Jürgen Becker 001; Reiner W. Hartenstein (J. Syst. Archit., 2003)

The digital divide of computing. - Reiner W. Hartenstein (Conf. Computing Frontiers, 2004)

Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic. - Mauricio Ayala-Rincón; Ricardo P. Jacobi; Luis Gustavo A. Carvalho; Carlos H. Llanos; Reiner W. Hartenstein (SBCCI, 2004)

The changing role of computer architecture education within CS curricula: invited presentation. - Reiner W. Hartenstein (WCAE, 2004)

Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming. - Ricardo P. Jacobi; Mauricio Ayala-Rincón; Luis Gustavo A. Carvalho; Carlos H. Llanos; Reiner W. Hartenstein (WOB, 2004)

FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. - Carlos Morra; Jürgen Becker 001; Mauricio Ayala-Rincón; Reiner W. Hartenstein (FPL, 2005)

Morphware and Configware. - Reiner W. Hartenstein (Handbook of Nature-Inspired and Innovative Computing, 2006)

From Organic Computing to Reconfigurable Supercomputing. - Reiner W. Hartenstein (ARCS Workshops, 2006)

From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. - Carlos Morra; M. Sackmann; Sunil Shukla; Jürgen Becker 001; Reiner W. Hartenstein (FPL, 2006)

RAW keynote 2: new horizons of very high performance computing (VHPC): hurdles and chances. - Reiner W. Hartenstein (IPDPS, 2006)

Flexibility and low power: a contradiction in terms? - Peter Wintermayr; Reiner W. Hartenstein; Heinrich Meyr; Steve Leibson (ISLPED, 2006)

Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. - Carlos Morra; M. Sackmann; Jürgen Becker 001; Reiner W. Hartenstein (ReCoSoC, 2006)

The re-definition of low power design for HPC: a paradigm shift. - Reiner W. Hartenstein (SBCCI, 2006)

Mehr Effizienz durch Configware: auch für Supercomputing. - Reiner W. Hartenstein (Prax. Inf.verarb. Kommun., 2006)

Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic. - Mauricio Ayala-Rincón; Carlos H. Llanos; Ricardo P. Jacobi; Reiner W. Hartenstein (ACM Trans. Design Autom. Electr. Syst., 2006)

The Neumann Syndrome calls for a revolution. - Reiner W. Hartenstein (HPRCTA, 2007)

The von Neumann Syndrome and the CS Education Dilemma. - Reiner W. Hartenstein (ARC, 2008)

The tunnel vision syndrome: Massively delaying progress. - Reiner W. Hartenstein (ASAP, 2013)