A memory-based high-speed digital delay line with a large adjustable length. - Hans Jürgen Mattausch; Fred Matthiesen; Jutta Hartl; Reinhard Tielert; Erwin P. Jacobs (IEEE J. Solid State Circuits, 1988)

A 0.11mm2 low-power A/D-converter cell for 10b 10MS/s operation. - David Muthers; Reinhard Tielert (ESSCIRC, 2004)

A Gb/s one-fourth-rate CMOS CDR circuit without external reference clock. - Sitt Tontisirin; Reinhard Tielert (ISCAS, 2006)

Low power UWB pulse radio transceiver front-end. - Muhammad Anis; Reinhard Tielert (ESSCIRC, 2007)

Gb/s CDR circuit for large synchronous networks. - Sitt Tontisirin; Reinhard Tielert (ESSCIRC, 2007)

Super-regenerative UWB impulse detector with synchronized quenching mechanism. - Muhammad Anis; Reinhard Tielert; Norbert Wehn (ESSCIRC, 2008)

3.1-to-7GHz UWB impulse radio transceiver front-end based on statistical correlation technique. - Muhammad Anis; Reinhard Tielert; Norbert Wehn (ISCAS, 2008)

Fully integrated self-quenched super-regenerative UWB impulse detector. - Muhammad Anis; Reinhard Tielert; Norbert Wehn (ISWPC, 2008)