Delay-Reduced Combinational Logic Synthesis using Multiplexers. - Rekha K. James; Shahana Thottathikkulam Kassim; K. Poulose Jacob; Sreela Sasi (ESA, 2006)

Genetic Algorithm-Based Combinational Logic Synthesis Using Universal Logic Modules. - Shahana Thottathikkulam Kassim; Rekha K. James; K. Poulose Jacob; Sreela Sasi (ESA, 2007)

A New Look at Reversible Logic Implementation of Decimal Adder. - Rekha K. James; Shahana Thottathikkulam Kassim; K. Poulose Jacob; Sreela Sasi (SoC, 2007)

RRNS-Convolutional encoded concatenated code for OFDM based wireless communication. - Shahana Thottathikkulam Kassim; Babita R. Jose; Rekha K. James; K. Poulose Jacob; Sreela Sasi (ICON, 2008)

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa. - Shahana Thottathikkulam Kassim; Babita R. Jose; Rekha K. James; K. Poulose Jacob; Sreela Sasi (ISCAS, 2008)

Fixed Point Decimal Multiplication Using RPS Algorithm. - Rekha K. James; Shahana Thottathikkulam Kassim; K. Poulose Jacob; Sreela Sasi (ISPA, 2008)

RNS Based Programmable Multi-Mode Decimation Filter for WCDMA and WiMAX. - Shahana Thottathikkulam Kassim; Babita R. Jose; Rekha K. James; K. Poulose Jacob; Sreela Sasi (VTC Spring, 2008)

Double Digit Decimal Multiplier on XILINX FPGA. - Rekha K. James; K. Poulose Jacob; Sreela Sasi (ESA, 2009)

High Performance, Low Latency Double Digit Decimal Multiplier on ASIC and FPGA. - Rekha K. James; K. Poulose Jacob; Sreela Sasi (NaBIC, 2009)

Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths. - Tuhin Subhra Chakraborty; Santanu Kundu; Deepak Agrawal; Sanjay Tanaji Shinde; Jacob Mathews; Rekha K. James (ACM Great Lakes Symposium on VLSI, 2016)

A GA Based Simple and Efficient Technique to Design Combinational Logic Circuits Using Universal Logic Modules. - C. K. Vijayakumari; Rekha K. James; P. Mythili (J. Circuits Syst. Comput., 2016)

ReDC: Reduced Deflection CHIPPER Router for Bufferless NoCs. - Rose George Kunthara; Rekha K. James; Simi Zerine Sleeba; John Jose (ISED, 2018)

Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip. - Simi Zerine Sleeba; John Jose; Maurizio Palesi; Rekha K. James; Maniyelil Govindankutty Mini (VLSI-SoC, 2018)

Token based Detection and Neural Network based Reconstruction framework against code injection vulnerabilities. - Teresa K. George; K. Poulose Jacob; Rekha K. James (J. Inf. Secur. Appl., 2018)

Asymmetric routing in 3D NoC using interleaved edge routers. - Rose George Kunthara; Rekha K. James; Simi Zerine Sleeba; John Jose (NoCArc@MICRO, 2019)

DoLaR: Double Layer Routing for Bufferless Mesh Network-on-Chip. - Rose George Kunthara; K. Neethu; Rekha K. James; Simi Zerine Sleeba; John Jose (TENCON, 2019)

2L-2D Routing for Buffered Mesh Network-on-Chip. - Rose George Kunthara; K. Neethu; Rekha K. James; Simi Zerine Sleeba; Tripti S. Warrier; John Jose (VDAT, 2019)

Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links. - S. Sharon Dev; S. M. Krishna; S. S. Archana; Rose George Kunthara; K. Neethu; Rekha K. James (VDAT, 2021)

Traffic aware routing in 3D NoC using interleaved asymmetric edge routers. - Rose George Kunthara; Rekha K. James; Simi Zerine Sleeba; John Jose (Nano Commun. Networks, 2021)

DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks. - Rose George Kunthara; Rekha K. James; Simi Zerine Sleeba; John Jose (ACM Great Lakes Symposium on VLSI, 2022)

RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC. - Akshay Sarman; Alwin Shaju; Rose George Kunthara; K. Neethu; Rekha K. James; John Jose (VLSI-SoC, 2022)

Threshold Voltage Modeling of Negative Capacitance Double Gate TFET. - U. S. Shikha; Rekha K. James; Anju Pradeep; Sumi Baby; Jobymol Jacob (VLSID, 2022)

Modelling and Impact Analysis of Push Back Attack in 3D Bufferless Network on Chip. - V. R. Josna; Rose George Kunthara; Rekha K. James; John Jose (MCSoC, 2023)

Modelling and Impact Analysis of Antipode Attack in Bufferless On-Chip Networks. - Rose George Kunthara; V. R. Josna; K. Neethu; Rekha K. James; John Jose (SN Comput. Sci., 2023)

ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training. - K. Neethu; K. C. Sharin Shahana; Rekha K. James; John Jose; Sumit K. Mandal (IEEE Des. Test, 2023)

Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-Chip. - Rose George Kunthara; Rekha K. James; Simi Zerine Sleeba; John Jose (J. Circuits Syst. Comput., 2024)