Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities. - Veeresh Deshpande; Sylvain Barraud; Xavier Jehl; Romain Wacquez; Maud Vinet; Remi Coquand; B. Roche; B. Voisin; François Triozon; C. Vizioz; L. Tosti; Bernard Previtali; et al. (ESSDERC, 2012)

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs. - Masahiro Koyama; Mikaël Cassé; Remi Coquand; Sylvain Barraud; Hiroshi Iwai; Gérard Ghibaudo; Gilles Reimbold (ESSDERC, 2012)

Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations. - Remi Coquand; Sylvain Barraud; Mikaël Cassé; Masahiro Koyama; Virginie Maffini-Alvaro; Marie-Pierre Samson; Lucie Tosti; Xavier Mescot; Gérard Ghibaudo; Stéphane Monfray; Frédéric Boeuf; Olivier Faynot; et al. (ESSDERC, 2013)

Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs. - Masahiro Koyama; Mikaël Cassé; Remi Coquand; Sylvain Barraud; Gérard Ghibaudo; Hiroshi Iwai; Gilles Reimbold (ESSDERC, 2013)