Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning. - Ghiath Al Sammane; Dominique Borrione; Remy Chevallier (ACM Great Lakes Symposium on VLSI, 2005)

Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata. - Remy Chevallier; Emmanuelle Encrenaz-Tiphène; Laurent Fribourg; Weiwen Xu (FORMATS, 2006)

Timed verification of the generic architecture of a memory circuit using parametric timed automata. - Remy Chevallier; Emmanuelle Encrenaz-Tiphène; Laurent Fribourg; Weiwen Xu (Formal Methods Syst. Des., 2009)

Formal Verification of Timed VHDL Programs. - Abdelrezzak Bara; Pirouz Bazargan-Sabet; Remy Chevallier; Dominique Le Dû; Emmanuelle Encrenaz; Patricia Renault (FDL, 2010)