A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits. - Jer-Min Jou; Shung-Chih Chen; Ren-Der Chen (ISCAS, 1994)

Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. - Jer-Min Jou; Ren-Der Chen; Shiann-Rong Kuang (ISCAS, 1994)

Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. - Ren-Der Chen; Jer-Min Jou; Yeu-Horng Shiau (ASP-DAC, 1999)

An efficient method for the decomposition and resynthesis of speed-independent circuits. - Ren-Der Chen; Jer-Min Jou; Yeu-Horng Shiau (ICECS, 1999)

Design of a dynamic pipelined architecture for fuzzy color correction. - Jer-Min Jou; Shiann-Rong Kuang; Yeu-Horng Shiau; Ren-Der Chen (IEEE Trans. Very Large Scale Integr. Syst., 2002)

An index coding algorithm for image vector quantization. - Pei-Yin Chen; Ren-Der Chen (IEEE Trans. Consumer Electron., 2003)

Hardware Implementation for a Genetic Algorithm. - Pei-Yin Chen; Ren-Der Chen; Yu-Pin Chang; Leang-San Shieh; Heidar A. Malki (IEEE Trans. Instrum. Meas., 2008)

Design of an Area-Efficient One-Dimensional Median Filter. - Ren-Der Chen; Pei-Yin Chen; Chun-Hsien Yeh (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Low-Power Architecture for the Design of a One-Dimensional Median Filter. - Ren-Der Chen; Pei-Yin Chen; Chun-Hsien Yeh (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A High-Performance Bidirectional Architecture for the Quasi-Comparison-Free Sorting Algorithm. - Wei-Ting Chen; Ren-Der Chen; Pei-Yin Chen; Yu-Che Hsiao (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)