Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign. - Ren-Jie Lee; Ming-Fang Lai; Hung-Ming Chen (ASP-DAC, 2007)

Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign. - Ren-Jie Lee; Hung-Ming Chen (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Row-based area-array I/O design planning in concurrent chip-package design flow. - Ren-Jie Lee; Hung-Ming Chen (ASP-DAC, 2011)

On routing fixed escaped boundary pins for high speed boards. - Tsung-Ying Tsai; Ren-Jie Lee; Ching-Yu Chin; Chung-Yi Kuan; Hung-Ming Chen; Yoji Kajitani (DATE, 2011)

Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign. - Ren-Jie Lee; Hung-Ming Chen (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A study of row-based area-array I/O design planning in concurrent chip-package design flow. - Ren-Jie Lee; Hung-Ming Chen (ACM Trans. Design Autom. Electr. Syst., 2013)

Board- and Chip-Aware Package Wire Planning. - Ren-Jie Lee; Hsin-Wu Hsu; Hung-Ming Chen (IEEE Trans. Very Large Scale Integr. Syst., 2013)