Parallelization and characterization of GARCH option pricing on GPUs. - Ren-Shuo Liu; Yun-Cheng Tsai; Chia-Lin Yang (IISWC, 2010)

Optimizing NAND flash-based SSDs via retention relaxation. - Ren-Shuo Liu; Chia-Lin Yang; Wei Wu (FAST, 2012)

DuraCache: a durable SSD cache using MLC NAND flash. - Ren-Shuo Liu; Chia-Lin Yang; Cheng-Hsuan Li; Geng-You Chen (DAC, 2013)

NVM duet: unified working memory and persistent store architecture. - Ren-Shuo Liu; De-Yu Shen; Chia-Lin Yang; Shun-Chih Yu; Cheng-Yuan Michael Wang (ASPLOS, 2014)

EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs. - Ren-Shuo Liu; Meng-Yen Chuang; Chia-Lin Yang; Cheng-Hsuan Li; Kin-Chu Ho; Hsiang-Pang Li (DAC, 2014)

Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality. - Ren-Shuo Liu; Meng-Yen Chuang; Chia-Lin Yang; Cheng-Hsuan Li; Kin-Chu Ho; Hsiang-Pang Li (IEEE Trans. Computers, 2016)

VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers. - Ren-Shuo Liu; Yun-Sheng Chang; Chih-Wen Hung (ICCAD, 2017)

DI-SSD: Desymmetrized interconnection architecture and dynamic timing calibration for solid-state drives. - Jian-Hao Huang; Ren-Shuo Liu (ASP-DAC, 2018)

A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array. - Pin-Yi Li; Cheng-Han Yang; Wei-Hao Chen; Jian-Hao Huang; Wei-Chen Wei; Je-Syu Liu; Wei-Yu Lin; Tzu-Hsiang Hsu; Chih-Cheng Hsieh; Ren-Shuo Liu; Meng-Fan Chang; Kea-Tiong Tang (BioCAS, 2018)

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors. - Wei-Hao Chen; Kai-Xiang Li; Wei-Yu Lin; Kuo-Hsiang Hsu; Pin-Yi Li; Cheng-Han Yang; Cheng-Xin Xue; En-Yu Yang; Yen-Kai Chen; Yun-Sheng Chang; Tzu-Hsiang Hsu; Ya-Chin King; et al. (ISSCC, 2018)

DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout. - Ren-Shuo Liu; Yun-Chen Lo; Yuan-Chun Luo; Chih-Yu Shen; Cheng-Ju Lee (VLSI-DAT, 2018)

AIP: Saving the DRAM Access Energy of CNNs Using Approximate Inner Products. - Cheng-Hsuan Cheng; Ren-Shuo Liu (AICAS, 2019)

A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction. - Tzu-Hsiang Hsu; Yen-Kai Chen; Tai-Hsing Wen; Wei-Chen Wei; Yi-Ren Chen; Fu-Chun Chang; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh (A-SSCC, 2019)

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. - Zhixiao Zhang; Jia-Jing Chen; Xin Si; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Yen-Cheng Chiu; Je-Min Hong; Shyh-Shyuan Sheu; Sih-Han Li; et al. (A-SSCC, 2019)

Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN). - Yun-Chen Lo; Yu-Chun Kuo; Yun-Sheng Chang; Jian-Hao Huang; Jun-Shen Wu; Wen-Chien Ting; Tai-Hsing Wen; Ren-Shuo Liu (ESSCIRC, 2019)

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. - Xin Si; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; Yen-Cheng Chiu; Wei-Chen Wei; Ssu-Yen Wu; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; et al. (ISSCC, 2019)

A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors. - Cheng-Xin Xue; Wei-Hao Chen; Je-Syu Liu; Jia-Fang Li; Wei-Yu Lin; Wei-En Lin; Jing-Hong Wang; Wei-Chen Wei; Ting-Wei Chang; Tung-Cheng Chang; Tsung-Yuan Huang; Hui-Yao Kao; et al. (ISSCC, 2019)

Long-Term JPEG Data Protection and Recovery for NAND Flash-Based Solid-State Storage. - Yu-Chun Kuo; Ruei-Fong Chiu; Ren-Shuo Liu (MSST, 2019)

OPTR: Order-Preserving Translation and Recovery Design for SSDs with a Standard Block Device Interface. - Yun-Sheng Chang; Ren-Shuo Liu (USENIX ATC, 2019)

Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices. - Kea-Tiong Tang; Wei-Chen Wei; Zuo-Wei Yeh; Tzu-Hsiang Hsu; Yen-Cheng Chiu; Cheng-Xin Xue; Yu-Chun Kuo; Tai-Hsing Wen; Mon-Shu Ho; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; et al. (VLSI Circuits, 2019)

5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel. - Tzu-Hsiang Hsu; Yen-Kai Chen; Jun-Shen Wu; Wen-Chien Ting; Cheng-Te Wang; Chen-Fu Yeh; Syuan-Hao Sie; Yi-Ren Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; et al. (ISSCC, 2020)

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Zhixiao Zhang; Syuan-Hao Sie; et al. (ISSCC, 2020)

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Zhixiao Zhang; Hongwu Jiang; et al. (ISSCC, 2020)

15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices. - Cheng-Xin Xue; Tsung-Yuan Huang; Je-Syu Liu; Ting-Wei Chang; Hui-Yao Kao; Jing-Hong Wang; Ta-Wei Liu; Shih-Ying Wei; Sheng-Po Huang; Wei-Chen Wei; Yi-Ren Chen; Tzu-Hsiang Hsu; et al. (ISSCC, 2020)

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. - Yen-Cheng Chiu; Zhixiao Zhang; Jia-Jing Chen; Xin Si; Ruhui Liu; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Je-Min Hung; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2020)

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. - Xin Si; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Qiang Li 021; Meng-Fan Chang; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; et al. (IEEE J. Solid State Circuits, 2020)

Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors. - Cheng-Xin Xue; Ting-Wei Chang; Tung-Cheng Chang; Hui-Yao Kao; Yen-Cheng Chiu; Chun-Ying Lee; Ya-Chin King; Chrong Jung Lin; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Wei-Hao Chen; et al. (IEEE J. Solid State Circuits, 2020)

A Bio-Inspired Motion Detection Circuit Model for the Computation of Optical Flow: The Spatial-Temporal Filtering Reichardt Model. - Hsin-Yu Wu; Wei-Tse Kao; Harrison Hao-Yu Ku; Cheng-Te Wang; Chih-Cheng Hsieh; Ren-Shuo Liu; Kea-Tiong Tang; Chung-Chuan Lo (AICAS, 2021)

Integer Quadratic Integrate-and-Fire (IQIF): A Neuron Model for Digital Neuromorphic Systems. - Wen-Chieh Wu; Chen-Fu Yeh; Alexander James White; Cheng-Te Wang; Zuo-Wei Yeh; Chih-Cheng Hsieh; Ren-Shuo Liu; Kea-Tiong Tang; Chung-Chuan Lo (AICAS, 2021)

Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators. - Jun-Shen Wu; Chi-En Wang; Ren-Shuo Liu (ASP-DAC, 2021)

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Tianlong Pan; Sih-Han Li; Shih-Chieh Chang; et al. (ISSCC, 2021)

A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices. - Cheng-Xin Xue; Je-Min Hung; Hui-Yao Kao; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Peng Chen; Ta-Wei Liu; Chuan-Jia Jhang; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; et al. (ISSCC, 2021)

A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel. - Tzu-Hsiang Hsu; Yen-Kai Chen; Min-Yang Chiu; Guan-Cheng Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2021)

A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction. - Tzu-Hsiang Hsu; Yi-Ren Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2021)

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Yen-Lin Chung; William Shih; et al. (IEEE J. Solid State Circuits, 2021)

ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators. - Yun-Chen Lo; Chih-Chen Yeh; Jun-Shen Wu; Chia-Chun Wang; Yu-Chih Tsai; Wen-Chien Ting; Ren-Shuo Liu (ICCAD, 2022)

A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations. - Yen-Cheng Chiu; Chia-Sheng Yang; Shih-Hsih Teng; Hsiao-Yu Huang; Fu-Chun Chang; Yuan Wu 009; Yu-An Chien; Fang-Ling Hsieh; Chung-Yuan Li; Guan-Yi Lin; Po-Jung Chen; Tsen-Hsiang Pan; et al. (ISSCC, 2022)

A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification. - Tzu-Hsiang Hsu; Guan-Cheng Chen; Yi-Ren Chen; Chung-Chuan Lo; Ren-Shuo Liu; Meng-Fan Chang; Kea-Tiong Tang; Chih-Cheng Hsieh (ISSCC, 2022)

An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices. - Je-Min Hung; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Tai-Hao Wen; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; et al. (ISSCC, 2022)

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (ISSCC, 2022)

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Yen-Lin Chung; Jin-Sheng Ren; et al. (IEEE J. Solid State Circuits, 2022)

Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference. - Yun-Chen Lo; Ren-Shuo Liu (DAC, 2023)

Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture. - Yun-Chen Lo; Ren-Shuo Liu (DAC, 2023)

Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory. - Yu-Chih Tsai; Wen-Chien Ting; Chia-Chun Wang; Chia-Cheng Chang; Ren-Shuo Liu (DATE, 2023)

BICEP: Exploiting Bitline Inversion for Efficient Operation-Unit-Based Compute-in-Memory Architecture: No Retraining Needed! - Yun-Chen Lo; Chia-Chun Wang; Ren-Shuo Liu (ICCD, 2023)

CNN Inference Accelerators with Adjustable Feature Map Compression Ratios. - Yu-Chih Tsai; Chung-Yueh Liu; Chia-Chun Wang; Tsen-Wei Hsu; Ren-Shuo Liu (ICCD, 2023)

Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators. - Chia-Chun Wang; Yun-Chen Lo; Jun-Shen Wu; Yu-Chih Tsai; Chia-Cheng Chang; Tsen-Wei Hsu; Min-Wei Chu; Chuan-Yao Lai; Ren-Shuo Liu (ICCD, 2023)

FM-P2L: An Algorithm Hardware Co-design of Fixed-Point MSBs with Power-of-2 LSBs in CNN Accelerators. - Jun-Shen Wu; Ren-Shuo Liu (ICCD, 2023)

Block and Subword-Scaling Floating-Point (BSFP) : An Efficient Non-Uniform Quantization For Low Precision Inference. - Yun-Chen Lo; Tse-Kuang Lee; Ren-Shuo Liu (ICLR, 2023)

A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices. - Yen-Cheng Chiu; Win-San Khwa; Chung-Yuan Li; Fang-Ling Hsieh; Yu-An Chien; Guan-Yi Lin; Po-Jung Chen; Tsen-Hsiang Pan; De-Qi You; Fang-Yi Chen; Andrew Lee; Chung-Chuan Lo; et al. (ISSCC, 2023)

A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W. - Wei-Hsing Huang; Tai-Hao Wen; Je-Min Hung; Win-San Khwa; Yun-Chen Lo; Chuan-Jia Jhang; Hung-Hsi Hsu; Yu-Hsiang Chin; Yu-Chiao Chen; Chuna-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; et al. (ISSCC, 2023)

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (ISSCC, 2023)

Bucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs. - Yun-Chen Lo; Ren-Shuo Liu (MICRO, 2023)

A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices. - Tai-Hao Wen; Je-Min Hung; Hung-Hsi Hsu; Yuan Wu 009; Fu-Chun Chang; Chung-Yuan Li; Chih-Han Chien; Chin-I Su; Win-San Khwa; Jui-Jen Wu; Chung-Chuan Lo; Ren-Shuo Liu; et al. (VLSI Technology and Circuits, 2023)

LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks. - Yun-Chen Lo; Yu-Chih Tsai; Ren-Shuo Liu (IEEE Comput. Archit. Lett., 2023)

8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices. - Je-Min Hung; Tai-Hao Wen; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; et al. (IEEE J. Solid State Circuits, 2023)

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Tianlong Pan; Chuan-Jia Jhang; Wei-Hsing Huang; et al. (IEEE J. Solid State Circuits, 2023)

A Multimode Vision Sensor With Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo Vision. - Min-Yang Chiu; Guan-Cheng Chen; Tzu-Hsiang Hsu; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2023)

A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification. - Tzu-Hsiang Hsu; Guan-Cheng Chen; Yi-Ren Chen; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh (IEEE J. Solid State Circuits, 2023)

SG-Float: Achieving Memory Access and Computing Power Reduction Using Self-Gating Float in CNNs. - Jun-Shen Wu; Tsen-Wei Hsu; Ren-Shuo Liu (ACM Trans. Embed. Comput. Syst., 2023)

34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices. - Win-San Khwa; Ping-Chun Wu; Jui-Jen Wu; Jian-Wei Su; Ho-Yu Chen; Zhao-En Ke; Ting-Chien Chiu; Jun-Ming Hsu; Chiao-Yen Cheng; Yu-Chen Chen; Chung-Chuan Lo; Ren-Shuo Liu; et al. (ISSCC, 2024)

34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices. - Tai-Hao Wen; Hung-Hsi Hsu; Win-San Khwa; Wei-Hsing Huang; Zhao-En Ke; Yu-Hsiang Chin; Hua-Jin Wen; Yu-Chen Chang; Wei-Ting Hsu; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; et al. (ISSCC, 2024)

A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro. - De-Qi You; Win-San Khwa; Jui-Jen Wu; Chuan-Jia Jhang; Guan-Yi Lin; Po-Jung Chen; Ting-Chien Chiu; Fang-Yi Chen; Andrew Lee; Yu-Cheng Hung; Chung-Chuan Lo; Ren-Shuo Liu; et al. (VLSI Technology and Circuits, 2024)

A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme. - Hung-Hsi Hsu; Tai-Hao Wen; Wei-Hsing Huang; Win-San Khwa; Yun-Chen Lo; Chuan-Jia Jhang; Yu-Hsiang Chin; Yu-Chiao Chen; Chung-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; Chih-Cheng Hsieh; et al. (IEEE J. Solid State Circuits, 2024)

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (IEEE J. Solid State Circuits, 2024)

An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices. - De-Qi You; Yen-Cheng Chiu; Win-San Khwa; Chung-Yuan Li; Fang-Ling Hsieh; Yu-An Chien; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; Tsung-Yung Jonathan Chang; et al. (IEEE J. Solid State Circuits, 2024)

8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. - Jian-Wei Su; Pei-Jung Lu; Ping-Chun Wu; Yen-Chi Chou; Ta-Wei Liu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Wei-Hsing Huang; Chih-Han Chien; Peng-I Mei; Sih-Han Li; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2024)

ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory. - Yun-Chen Lo; Jun-Shen Wu; Chia-Chun Wang; Yu-Chih Tsai; Chih-Chen Yeh; Wen-Chien Ting; Ren-Shuo Liu (IEEE Trans. Computers, 2024)

14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices. - Win-San Khwa; Ping-Chun Wu; Jian-Wei Su; Chiao-Yen Cheng; Jun-Ming Hsu; Yu-Chen Chen; Le-Jung Hsieh; Jyun-Cheng Bai; Yu-Sheng Kao; Tsung-Han Lou; Ashwin Sanjay Lele; Jui-Jen Wu; et al. (ISSCC, 2025)

14.1 A 22nm 104.5TOPS/W µ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks. - De-Qi You; Win-San Khwa; Bo Zhang; Fang-Yi Chen; Andrew Lee; Yu-Cheng Hung; Yi-Ming Li; Yu-Hui Wang; Chung-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; Chih-Cheng Hsieh; et al. (ISSCC, 2025)

A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device. - Hung-Hsi Hsu; Tai-Hao Wen; Win-San Khwa; Wei-Hsing Huang; Zhao-En Ke; Yu-Hsiang Chin; Hua-Jin Wen; Yu-Chen Chang; Wei-Ting Hsu; Ashwin Sanjay Lele; Bo Zhang; Ping-Sheng Wu; et al. (IEEE J. Solid State Circuits, 2025)

An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips. - Ping-Chun Wu; Win-San Khwa; Jui-Jen Wu; Jian-Wei Su; Chuan-Jia Jhang; Ho-Yu Chen; Zhao-En Ke; Ting-Chien Chiu; Jun-Ming Hsu; Chiao-Yen Cheng; Yu-Chen Chen; Chung-Chuan Lo; et al. (IEEE J. Solid State Circuits, 2025)