Proud: A Fast Sea-of-Gates Placement Algorithm. - Ren-Song Tsay; Ernest S. Kuh; Chi-Ping Hsu (DAC, 1988)

PROUD: a sea-of-gates placement algorithm. - Ren-Song Tsay; Ernest S. Kuh; Chi-Ping Hsu (IEEE Des. Test, 1988)

A new approach to sea-of-gates global routing. - Tai-Ming Parng; Ren-Song Tsay (ICCAD, 1989)

Floorplanning by Topological Constraint Reduction. - Gopalakrishnan Vijayan; Ren-Song Tsay (ICCAD, 1990)

An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement. - Ren-Song Tsay; Jürgen Koehl (DAC, 1991)

Exact Zero Skew. - Ren-Song Tsay (ICCAD, 1991)

A new method for floor planning using topological constraint reduction. - Gopalakrishnan Vijayan; Ren-Song Tsay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Performance-Driven System Partitioning on Multi-Chip Modules. - Minshine Shih; Ernest S. Kuh; Ren-Song Tsay (DAC, 1992)

Clock tree regeneration. - Jan-Ming Ho; Ren-Song Tsay (Great Lakes Symposium on VLSI, 1992)

An exact zero-skew clock routing algorithm. - Ren-Song Tsay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

An Entrepreneurship Emulation Platform. - Ren-Song Tsay (MSE, 2007)

Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video. - Ching-Te Chiu; Tsun-Hsien Wang; Wei-Ming Ke; Chen-Yu Chuang; Jhih-Rong Chen; Rong Yang; Ren-Song Tsay (ICIP, 2008)

A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology. - Ching-Te Chiu; Tsun-Hsien Wang; Wei-Ming Ke; Chen-Yu Chuang; Jhih-Siao Huang; Wei-Su Wong; Ren-Song Tsay (SiPS, 2008)

Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model. - Chen Kang Lo; Ren-Song Tsay (ASP-DAC, 2009)

Cycle count accurate memory modeling in system level design. - Yi-Len Lo; Mao Lin Li; Ren-Song Tsay (CODES+ISSS, 2009)

An effective synchronization approach for fast and accurate multi-core instruction-set simulation. - Meng-Huan Wu; Cheng-Yang Fu; Peng-Chih Wang; Ren-Song Tsay (EMSOFT, 2009)

How to consider shorts and guarantee yield rate improvement for redundant wire insertion. - Fong-Yuan Chang; Ren-Song Tsay; Wai-Kei Mak (ICCAD, 2009)

Source-level timing annotation for fast and accurate TLM computation model generation. - Kai-Li Lin; Chen Kang Lo; Ren-Song Tsay (ASP-DAC, 2010)

Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation. - Meng-Huan Wu; Wen-Chuan Lee; Chen-Yu Chuang; Ren-Song Tsay (DATE, 2010)

Cut-demand based routing resource allocation and consolidation for routability enhancement. - Fong-Yuan Chang; Sheng-Hsiung Chen; Ren-Song Tsay; Wai-Kei Mak (ASP-DAC, 2011)

A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation. - Meng-Huan Wu; Peng-Chih Wang; Cheng-Yang Fu; Ren-Song Tsay (DAC, 2011)

A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems. - Cheng-Yang Fu; Meng-Huan Wu; Ren-Song Tsay (DATE, 2011)

Cycle-count-accurate processor modeling for fast and accurate system-level simulation. - Chen Kang Lo; Li-Chun Chen; Meng-Huan Wu; Ren-Song Tsay (DATE, 2011)

DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive scheduling. - Peng-Chih Wang; Meng-Huan Wu; Ren-Song Tsay (DATE, 2011)

From academic ideas to practical physical design tools. - Ren-Song Tsay (ISPD, 2011)

Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform. - Ching-Te Chiu; Tsun-Hsien Wang; Wei-Ming Ke; Chen-Yu Chuang; Jhih-Siao Huang; Wei-Su Wong; Ren-Song Tsay; Cyuan-Jhe Wu (J. Signal Process. Syst., 2011)

A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation. - Yu-Hung Huang; Yi-Shan Lu; Hsin-I Wu; Ren-Song Tsay (DAC, 2012)

An Extended SystemC Framework for Efficient HW/SW Co-Simulation. - Meng-Huan Wu; Peng-Chih Wang; Cheng-Yang Fu; Ren-Song Tsay (ACM Trans. Design Autom. Electr. Syst., 2012)

A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules. - Fong-Yuan Chang; Ren-Song Tsay; Wai-Kei Mak; Sheng-Hsiung Chen (ASP-DAC, 2013)

An efficient hybrid synchronization technique for scalable multi-core instruction set simulations. - Bo-Han Zeng; Ren-Song Tsay; Ting-Chi Wang (ASP-DAC, 2013)

A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations. - Fan-Wei Yu; Bo-Han Zeng; Yu-Hung Huang; Hsin-I Wu; Che-Rung Lee; Ren-Song Tsay (DATE, 2013)

A Cycle Count Accurate TLM bus modeling approach. - Mao Lin Li; Chen Kang Lo; Li-Chun Chen; Jen-Chieh Yeh; Ren-Song Tsay (VLSI-DAT, 2013)

A fast and accurate instruction-oriented processor simulation approach. - Pei-Chia Patty Lin; Evason Du; Ren-Song Tsay (VLSI-DAT, 2013)

A basic-block power annotation approach for fast and accurate embedded software power estimation. - Chien-Min Lee; Chi-Kang Chen; Ren-Song Tsay (VLSI-SoC, 2013)

MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules. - Fong-Yuan Chang; Ren-Song Tsay; Wai-Kei Mak; Sheng-Hsiung Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus. - Chen Kang Lo; Mao Lin Li; Li-Chun Chen; Yi-Shan Lu; Ren-Song Tsay; Hsu-Yao Huang; Jen-Chieh Yeh (ACM Trans. Embed. Comput. Syst., 2013)

A distributed timing synchronization technique for parallel multi-core instruction-set simulation. - Meng-Huan Wu; Cheng-Yang Fu; Peng-Chih Wang; Ren-Song Tsay (ACM Trans. Embed. Comput. Syst., 2013)

An activity-sensitive contention delay model for highly efficient deterministic full-system simulations. - Shu-Yung Chen; Chien-Hao Chen; Ren-Song Tsay (DATE, 2014)

Automatic timing-coherent transactor generation for mixed-level simulations. - Li-Chun Chen; Hsin-I Wu; Ren-Song Tsay (ASP-DAC, 2015)

AROMA: A highly accurate microcomponent-based approach for embedded processor power analysis. - Zih-Ci Huang; Chi-Kang Chen; Ren-Song Tsay (ASP-DAC, 2015)

Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations. - Jyun-Hao Chang; Hsin-I Wu; Hsien-Lun Pai; Ren-Song Tsay; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

An accurate and flexible early memory system power evaluation approach using a microcomponent method. - Chi-Kang Chen; Hsin-I Wu; Chi-Ting Hsiao; Ren-Song Tsay (CODES+ISSS, 2016)

Poster Paper: An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. - Hsuan-Man Chen; Chi-Kang Chen; Hsin-I Wu; Ren-Song Tsay (ICHI, 2016)

An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. - Hsuan-Man Chen; Chi-Kang Chen; Hsin-I Wu; Ren-Song Tsay (ICHI, 2016)

A highly efficient full-system virtual prototype based on virtualization-assisted approach. - Hsin-I Wu; Chi-Kang Chen; Tsung-Ying Lu; Ren-Song Tsay (DATE, 2018)

A Pipeline-Based Scheduler for Optimizing Latency of Convolution Neural Network Inference over Heterogeneous Multicore Systems. - Hsin-I Wu; Da-Yi Guo; Hsu-Hsun Chin; Ren-Song Tsay (AICAS, 2020)

Designing A Compact Convolutional Neural Network Processor on Embedded FPGAs. - Yin-Chun Ling; Hsu-Hsun Chin; Hsin-I Wu; Ren-Song Tsay (GCAIoT, 2020)

An Optimal Slack-Based Course Scheduling Algorithm for Personalised Study Plans. - Asheen Lateilla Richards; Ren-Song Tsay (ICEIT, 2020)

A Heuristic Region-based Concurrency Bug Testing Approach. - Kuo-Cheng Chin; Ren-Song Tsay; Hsin-I Wu (ISPA/BDCloud/SocialCom/SustainCom, 2020)

VIRA: a virtualization assisted deterministic system-level simulations. - Hsin-I Wu; Ren-Song Tsay; Hsu-Hsun Chin (SAC, 2020)

CORONA: A k-COnnected RObust Interconnection Network Generation Algorithm. - Hsin-I Wu; Ren-Song Tsay; Fong-Yuan Chang (VLSI-DAT, 2020)

A Very Compact Embedded CNN Processor Design Based on Logarithmic Computing. - Tsung-Ying Lu; Hsu-Hsun Chin; Hsin-I Wu; Ren-Song Tsay (CoRR, 2020)

A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Intercomponent Interactions. - Hsin-I Wu; Da-Yi Guo; Ren-Song Tsay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A High-Performance Adaptive Quantization Approach for Edge CNN Applications. - Hsu-Hsun Chin; Ren-Song Tsay; Hsin-I Wu (CoRR, 2021)

An Effective Parallel Program Debugging Approach Based on Timing Annotation. - Yun Chang; Hsin-I Wu; Ren-Song Tsay (CoRR, 2021)

Analytical Process Scheduling Optimization for Heterogeneous Multi-core Systems. - Chien-Hao Chen; Ren-Song Tsay (CoRR, 2021)

A Fast-and-Effective Early-Stage Multi-level Cache Optimization Method Based on Reuse-Distance Analysis. - Cheng-Lin Tsai; Ren-Song Tsay (CoRR, 2021)

An Effective Early Multi-core System Shared Cache Design Method Based on Reuse-distance Analysis. - Hsin-Yu Ho; Ren-Song Tsay (CoRR, 2021)

A Precise Program Phase Identification Method Based on Frequency Domain Analysis. - Hsuan-Yi Lin; Ren-Song Tsay (CoRR, 2021)

A Double-Linked Blockchain Approach Based on Proof-of-Refundable-Tax Consensus Algorithm. - Zheng-Xun Jiang; Ren-Song Tsay (CoRR, 2021)

3LSAA: A Secure And Privacy-preserving Zero-knowledge-based Data-sharing Approach Under An Untrusted Environment. - Wei-Yi Kuo; Ren-Song Tsay (CoRR, 2021)

An Adaptive High-Performance Quantization Approach for Resource-Constrained CNN Inference. - Hsu-Hsun Chin; Ren-Song Tsay; Hsin-I Wu (AICAS, 2022)

An Embedded CNN Design for Edge Devices Based on Logarithmic Computing. - Chong-Yin Lu; Ren-Song Tsay; Weyshin Chang (VLSI-DAT, 2022)

An Owner-managed Indirect-Permission Social Authentication Method for Private Key Recovery. - Wei-Hsin Chang; Ren-Song Tsay (CoRR, 2022)

A Secure and Reliable Private Key Recovery Method. - Wei-Hsin Chang; Ren-Song Tsay (ICCE-Taiwan, 2023)

Ureka: A Decentralized and Secure System for Managing Personal IoT Devices. - Yi-Chun Yang; Ren-Song Tsay (ICCE-Taiwan, 2023)

A Decentralized Solution for Secure Management of IoT Access Rights. - Yi-Chun Yang; Ren-Song Tsay (ICR, 2023)

Accelerate Large Language Model Inference on Edge TPU with OpenVX framework. - You-En Wu; Hsin-I Wu; Kuo-Cheng Chin; Yi-Chun Yang; Ren-Song Tsay (AICAS, 2024)

Beyond Time-Quantum: A Basic-Block FDA Approach for Accurate System Computing Performance Estimation. - Hsuan-Yi Lin; Ren-Song Tsay (ASPDAC, 2024)

A Secure Decentralized Key Backup and Social Recovery Method. - Nian-Zu Wang; Ren-Song Tsay (ICCE-Taiwan, 2024)