Systematischer Entwurf und Modellbildung systolischer Arrays. - Renate Merker (1990)

Systematic Generation of a Variety of Processor Arrays. - A. Schubert; Renate Merker; H. Schreiber (Parcella, 1994)

Propagation of I/O-Variables in Massively Parallel Processor Arrays. - Dirk Fimmel; Renate Merker (PDP, 1996)

Scheduling in Co-Partitioned Array Architectures. - Uwe Eckhardt; Renate Merker (ASAP, 1997)

Determination of the Processor Functionality in the Design of Processor Arrays. - Dirk Fimmel; Renate Merker (ASAP, 1997)

A System for Designing Parallel Processor Arrays. - Renate Merker; Ulrich Eckhardt; Dirk Fimmel; H. Schreiber (EUROCAST, 1997)

Optimization of the Background Memory Utilization by Partitioning. - Uwe Eckhardt; Renate Merker (ISSS, 1997)

Design of Processor Arrays for Real-Time Applications. - Dirk Fimmel; Renate Merker (Euro-Par, 1998)

Determination of processor allocation in the design of processor arrays. - Dirk Fimmel; Renate Merker (Microprocess. Microsystems, 1998)

Parallel Processor Array for Tomographic Reconstruction Algorithms. - Thomas Schmitt 002; Dirk Fimmel; Mathias Kortke; Renate Merker (EUROCAST, 1999)

Parallelization of Algorithms for a System of Digital Signal Processors. - Mathias Kortke; Dirk Fimmel; Renate Merker (EUROMICRO, 1999)

Localization of Data Transfer in Processor Arrays. - Dirk Fimmel; Renate Merker (Euro-Par, 1999)

Hierarchical algorithm partitioning at system level for an improved utilization of memory structures. - Uwe Eckhardt; Renate Merker (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Application of Partitioning Methods for the Design of Parallel Programs for a System of Digital Signal Processors. - Mathias Kortke; Thomas Schmitt 002; Renate Merker (PARELEC, 2000)

High-Level Synthesis System (HLDESA) for Processor Arrays. - Renate Merker (PARELEC, 2000)

Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel. - Rainer Schaffer; Francky Catthoor; Renate Merker (Parallel Algorithms Appl., 2000)

Design of Processor Arrays for Reconfigurable Architectures. - Dirk Fimmel; Renate Merker (J. Supercomput., 2001)

Systematic Design of Programs with Sub-Word Parallelism. - Rainer Schaffer; Renate Merker; Francky Catthoor (PARELEC, 2002)

Causality Constraints for Processor Architectures with Sub-Word Parallelism. - Rainer Schaffer; Renate Merker; Francky Catthoor (DSD, 2003)

A Hardware-Software System for Tomographic Reconstruction. - Jan Müller 001; Dirk Fimmel; Renate Merker; Rainer Schaffer (J. Circuits Syst. Comput., 2003)

Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling. - Jan Müller 001; Dirk Fimmel; Renate Merker (Interaction between Compilers and Computer Architectures, 2004)

Optimized Data-Reuse in Processor Arrays. - Sebastian Siegel; Renate Merker (ASAP, 2004)

Optimal Loop Scheduling with Register Constraints Using Flow Graphs. - Jan Müller 001; Dirk Fimmel; Renate Merker (ISPAN, 2004)

A Parallel Hardware-Software System for Signal Processing Algorithms. - Mathias Kortke; Jan Müller 001; Rainer Schaffer; Sebastian Siegel; Renate Merker; Jürgen Kelber (PARELEC, 2004)

Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays. - Sebastian Siegel; Renate Merker (PARELEC, 2004)

Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching. - Markus Rullmann; Sebastian Siegel; Renate Merker (IPDPS, 2005)

Co-Design of Massively Parallel Embedded Processor Architectures. - Frank Hannig; Hritam Dutta; Alexey Kupriyanov; Jürgen Teich; Rainer Schaffer; Sebastian Siegel; Renate Merker; Ronan Keryell; Bernard Pottier; Daniel Chillet; Daniel Ménard; Olivier Sentieys (ReCoSoC, 2005)

Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration Overhead. - Markus Rullmann; Renate Merker (ARCS Workshops, 2006)

Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy. - Sebastian Siegel; Renate Merker (ASAP, 2006)

Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints. - Sebastian Siegel; Renate Merker (Euro-Par, 2006)

Maximum edge matching for reconfigurable computing. - Markus Rullmann; Renate Merker (IPDPS, 2006)

An Architecture Description Language for Massively Parallel Processor Architectures. - Alexey Kupriyanov; Frank Hannig; Dmitrij Kissler; Jürgen Teich; Rainer Schaffer; Renate Merker (MBMV, 2006)

Derivation of Packing Instructions for Exploiting Sub-Word Parallelism. - Rainer Schaffer; Renate Merker; Francky Catthoor (PARELEC, 2006)

Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels. - Sebastian Siegel; Rainer Schaffer; Renate Merker (PARELEC, 2006)

Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism. - Rainer Schaffer; Renate Merker (ICSAMOS, 2006)

A Reconfiguration Aware Circuit Mapper for FPGAs. - Markus Rullmann; Renate Merker (IPDPS, 2007)

Massively Parallel Processor Architectures: A Co-design Approach. - Hritam Dutta; Frank Hannig; Alexey Kupriyanov; Dmitrij Kissler; Jürgen Teich; Rainer Schaffer; Sebastian Siegel; Renate Merker; Bernard Pottier (ReCoSoC, 2007)

Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. - Rainer Schaffer; Renate Merker; Frank Hannig; Jürgen Teich (DSD, 2008)

Fine grain reconfigurable architectures. - Josef Angermeier; Mateusz Majer; Jürgen Teich; Lars Braun; Tobias Schwalb; Philipp Graf; Michael Hübner 001; Jürgen Becker 001; Enno Lübbers; Marco Platzner; Christopher Claus; Walter Stechele; et al. (FPL, 2008)

Synthesis of efficiently reconfigurable datapaths for reconfigurable computing. - Markus Rullmann; Renate Merker (FPT, 2008)

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. - Markus Rullmann; Renate Merker; Heiko Hinkelmann; Peter Zipf; Manfred Glesner (FPL, 2009)

Design Methods and Tools for Improved Partial Dynamic Reconfiguration. - Markus Rullmann; Renate Merker (Dynamically Reconfigurable Systems, 2010)

A Cost Model for Partial Dynamic Reconfiguration. - Markus Rullmann; Renate Merker (Trans. High Perform. Embed. Archit. Compil., 2011)