Some Parallel Thinning Algorithms for Digital Pictures. - Renato Stefanelli; Azriel Rosenfeld (J. ACM, 1971)

A Suggestion for a High-Speed Parallel Binary Divider. - Renato Stefanelli (IEEE Trans. Computers, 1972)

Compression algorithms that preserve basic topological features in binary-coded patterns. - Mariagiovanna Sami; Renato Stefanelli (Pattern Recognit., 1973)

A multiplier with multiple error correction capability. - Marco Annaratone; Renato Stefanelli (IEEE Symposium on Computer Arithmetic, 1983)

PAPIA: Pyramidal architecture for parallel image analysis. - Virginio Cantoni; Marco Ferretti; Stefano Levialdi; Renato Stefanelli (IEEE Symposium on Computer Arithmetic, 1985)

Fault Tolerance Fechniques for Array Structures Used in Supercomputing. - Roberto M. Negrini; Mariagiovanna Sami; Renato Stefanelli (Computer, 1986)

Reconfigurable architectures for VLSI processing arrays. - Mariagiovanna Sami; Renato Stefanelli (Proc. IEEE, 1986)

A comment on an investigation into the skeletonization approach of Hilditch. - Renato Stefanelli (Pattern Recognit., 1986)

A Technique for Reconfiguring Two Dimensional VLSI Arrays. - Fabrizio Lombardi; Donatella Sciuto; Renato Stefanelli (RTSS, 1987)

Use of redundant binary representation for fault-tolerant arithmetic array processors. - Vincenzo Piuri; Renato Stefanelli (ICCD, 1988)

Error detection in serial multipliers and in systolic arrays: An approach based upon A★N codes. - Vincenzo Piuri; Renato Stefanelli; Giovanni Traverso (Microprocess. Microprogramming, 1988)

An algorithm for functional reconfiguration of fixed-size arrays. - Fabrizio Lombardi; Donatella Sciuto; Renato Stefanelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Fault-tolerance through reconfiguration of VLSI and WSI awards. - Roberto M. Negrini; Mariagiovanna Sami; Renato Stefanelli (MIT Press, 1989)

Reconfiguration of VLSI arrays by covering. - Fabrizio Lombardi; Mariagiovanna Sami; Renato Stefanelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Area compaction in silicon structures for neural net implementation. - Fausto Distante; M. G. Sami; Renato Stefanelli; Giancarlo Storti Gajani (Microprocessing and Microprogramming, 1990)

Optimization techniques for multiple output function synthesis. - Giacomo Buonanno; Donatella Sciuto; Renato Stefanelli (EURO-DAC, 1991)

Concurrent error detection in parallel multipliers and complex arithmetic structures: Remarks on the use of the 3n code. - Vincenzo Piuri; Renato Stefanelli (Microprocessing and Microprogramming, 1991)

Mapping neural nets onto a massively parallel architecture: a defect-tolerance solution. - Fausto Distante; Mariagiovanna Sami; Renato Stefanelli; Giancarlo Storti-Gajan (Proc. IEEE, 1991)

The PAPIA system. - Virginio Cantoni; V. Gesu; Marco Ferretti; Stefano Levialdi; Roberto M. Negrini; Renato Stefanelli (J. VLSI Signal Process., 1991)

Fault-tolerant techniques for VLSI tree structures. - Vincenzo Piuri; Renato Stefanelli (Microprocess. Microprogramming, 1992)

A behavioral approach to testability analysis for neural networks. - Vincenzo Piuri; Mariagiovanna Sami; Donatella Sciuto; Renato Stefanelli (Microprocess. Microprogramming, 1992)

Multi-parallel convolvers. - Luigi Dadda; Vincenzo Piuri; Renato Stefanelli (IEEE Symposium on Computer Arithmetic, 1993)

System Level Policies for Fault Tolerance Issues in the FERMI Project. - A. Dell'Acqua; M. Hansen; Sami J. Inkinen; B. Lofstedt; J. P. Vanuxem; Christer Svensson; Jiren Yuan; H. Hentzell; L. Del Buono; J. David; J. F. Genat; H. Lebbolo; et al. (DFT, 1993)

New CMOS Structures for the Synthesis of Dominant Functions. - Giacomo Buonanno; Donatella Sciuto; Renato Stefanelli (VLSI Design, 1993)

Concurrently self-checking structures for Fsms. - M. G. Sami; Donatella Sciuto; Renato Stefanelli (Microprocess. Microprogramming, 1993)

A CMOS Fault Tolerant Architecture for Swith-Level Faults. - Cristiana Bolchini; Giacomo Buonanno; Donatella Sciuto; Renato Stefanelli (DFT, 1994)

CMOS Reliability Improvements Through a New Fault Tolerant Technique. - Cristiana Bolchini; Giacomo Buonanno; Donatella Sciuto; Renato Stefanelli (ISCAS, 1994)

Innovative Structures for CMOS Combinational Gates Synthesis. - Giacomo Buonanno; Donatella Sciuto; Renato Stefanelli (IEEE Trans. Computers, 1994)

A Channel-Constrained Reconfiguration Approach for Processing Arrays. - Mariagiovanna Sami; Fausto Distante; Renato Stefanelli (DFT, 1995)

A new switching-level approach to multiple-output functions synthesis. - Cristiana Bolchini; Giacomo Buonanno; Donatella Sciuto; Renato Stefanelli (VLSI Design, 1995)

Fault detection and fault tolerance issues at CMOS level through AUED encoding. - Cristiana Bolchini; Giacomo Buonanno; Donatella Sciuto; Renato Stefanelli (DFT, 1996)

KITE: a behavioural approach to fault-tolerance in FPGA-based systems. - Giovanni A. Mojoli; Davide Salvi; M. G. Sami; Giacomo R. Sechi; Renato Stefanelli (DFT, 1996)

Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks. - Cristiana Bolchini; Giacomo Buonanno; M. Cozzini; Donatella Sciuto; Renato Stefanelli (DFT, 1997)

Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance. - Fausto Distante; Mariagiovanna Sami; Renato Stefanelli (DFT, 1997)

Array partitioning to achieve defect tolerance. - Fausto Distante; Mariagiovanna Sami; Renato Stefanelli (EUROMICRO, 1997)

Systematic AUED Codes for Self-Checking Architectures. - Donatella Sciuto; Cristina Silvano; Renato Stefanelli (DFT, 1998)

Fault-Tolerant CAM Architectures: A Design Framework. - Fabio Salice; Mariagiovanna Sami; Renato Stefanelli (DFT, 2002)

A New Compact SD2 Positive Integer Triangular Array Division Circuit. - Marco D. Santambrogio; Renato Stefanelli (IEEE Trans. Very Large Scale Integr. Syst., 2011)